A High-Speed Computational Pipeline Single MAC-Based VLSI Architecture for Real-Time Signal and Image Processing

Vaithiyanathan, Dhandapani; James, Britto Pari; Mariammal, Karuthapandian

doi:10.1109/icaect60202.2024.10469571

2024 Fourth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT) 2024

DOI: 10.1109/icaect60202.2024.10469571

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A High-Speed Computational Pipeline Single MAC-Based VLSI Architecture for Real-Time Signal and Image Processing

Dhandapani Vaithiyanathan,

Britto Pari James,

Karuthapandian Mariammal

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Vaithiyanathan

2024

2024 First International Conference on Innovations in Communications, Electrical and Computer Engineering (ICICEC)

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Study and Experimental Analysis of FIR Hardware Architecture for Real-time Multimedia Applications

Vaithiyanathan

2024

2024 First International Conference on Innovations in Communications, Electrical and Computer Engineering (ICICEC)

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A High-Speed Computational Pipeline Single MAC-Based VLSI Architecture for Real-Time Signal and Image Processing

Cited by 1 publication

References 26 publications

Study and Experimental Analysis of FIR Hardware Architecture for Real-time Multimedia Applications

Study and Experimental Analysis of FIR Hardware Architecture for Real-time Multimedia Applications

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