A High Speed Hardware Scheduler for 1000-Port Optical Packet Switches to Enable Scalable Data Centers

Abstract

Meeting the exponential increase in the global demand for bandwidth has become a major concern for today's data centers. The scalability of any data center is defined by the maximum capacity and port count of the switching devices it employs, limited by total pin bandwidth on current electronic switch ASICs. Optical switches can provide higher capacity and port counts, and hence, can be used to transform data center scalability. We have recently demonstrated a 1000-port starcoupler based wavelength division multiplexed (WDM) and time division multiplexed (TDM) optical switch architecture offering a bandwidth of 32 Tbit/s with the use of fast wavelength-tunable transmitters and high-sensitivity coherent receivers. However, the major challenge in deploying such an optical switch to replace current electronic switches lies in designing and implementing a scalable scheduler capable of operating on packet timescales. In this paper, we present a pipelined and highly parallel electronic scheduler that configures the high-radix (1000-port) optical packet switch. The scheduler can process requests from 1000 nodes and allocate timeslots across 320 wavelength channels and 4000 wavelength-tunable transceivers within a time constraint of 1µs. Using the Opencell NanGate 45nm standard cell library, we show that the complete 1000-port parallel scheduler algorithm occupies a circuit area of 52.7mm 2 , 4-8x smaller than that of a high-performance switch ASIC, with a clock period of less than 8ns, enabling 138 scheduling iterations to be performed in 1µs. The performance of the scheduling algorithm is evaluated in comparison to maximal matching from graph theory and conventional software-based wavelength allocation heuristics. The parallel hardware scheduler is shown to achieve similar matching performance and network throughput while being orders of magnitude faster.

Hybrid Wavelength Switched-TDMA High Port Count All-Optical Data Centre Switch

“…In this switch, there is no central buffering and the latency through the data plane from transmitter to receiver is dictated only by the speed of light. While the network scheduler may add latency (not the focus of this work, but practical scheduling algorithms for this design are under development [24]), there is room for considerable scheduling delay before this system would show the same performance, particularly in terms of worst case tail latency, as an electrical network reaching a high port count. Figure 7 shows the experimental setup.…”

An Optimum Lower Bound for the Weights of Maximum Weight Matching in Bipartite Graphs

“…This result can be applied to develop optical packet switches to transform data center scalability [1]. It is also applicable to the area of stringology [7,10].…”

Parallel Star-coupler OCS Architectures using Distributed Hardware Schedulers

“…At the end of every epoch, failed requests are stored in a 128kB buffer and the switch configuration matrix is sent to the nodes to tune transceivers to relevant wavelengths. The 1000-port hardware was shown to occupy an ASIC area of 52.7 mm 2 , when synthesized on 45nm NanGate Opencell CMOS library, meeting timing at a clock period of 7.2ns [3]. The scheduler algorithm has the following improvements compared to previous work presented in [3].…”

“…The 1000-port hardware was shown to occupy an ASIC area of 52.7 mm 2 , when synthesized on 45nm NanGate Opencell CMOS library, meeting timing at a clock period of 7.2ns [3]. The scheduler algorithm has the following improvements compared to previous work presented in [3]. A novel buffer system is introduced and in every epoch, scheduler gives priority to buffers than requests.…”

“…Nevertheless, reconfiguring the switch requires a fast and scalable controller. Hence, we proposed a novel parallel hardware scheduler design for a 1000-server optical switch that computes schedules in microsecond timescales [3].…”