A High-Throughput Maximum<i>a Posteriori</i>Probability Detector

Ratnayake, R.; Kavcic, A.; Wei, Gu-Yeon

doi:10.1109/jssc.2008.925404

Cited by 9 publications

(1 citation statement)

References 36 publications

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“…MAP decoder architectures have been studied by many researchers [24,25,[32][33][34][35]. Several factors, such as interleaver structure and sliding window scheme, must be considered when choosing an appropriate MAP decoder for LTE Turbo decoding.…”

Section: Map Decoder Architecture For Lte Turbo Codesmentioning

confidence: 99%

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun

Cavallaro

2011

Integration

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a b s t r a c tWe present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The highthroughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations &

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Section: Map Decoder Architecture For Lte Turbo Codesmentioning

confidence: 99%

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun

Cavallaro

2011

Integration

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Monte Carlo analysis of a low power domino gate under parameter fluctuation

Wang

Gong

et al. 2009

J. Semicond.

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Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique (DTV) in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.

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Effectiveness analysis of low power technique of dynamic logic under temperature and process Variations

Wang

Gong

et al. 2009

2009 IEEE 8th International Conference on ASIC

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A High-Throughput Maximuma PosterioriProbability Detector

Cited by 9 publications

References 36 publications

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Monte Carlo analysis of a low power domino gate under parameter fluctuation

Effectiveness analysis of low power technique of dynamic logic under temperature and process Variations

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