A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond

Weis, R.; Hummler, Klaus; Akatsu, H.; Kudelka, S.; Dyer, T.; Seitz, Michelle E.; Scholz, Albrecht; Kim, B.; Wise, M. L. H.; Malik, R.; Strane, J.; Goebel, T.; McStay, K.; Beintner, J.; Arnold, N.; Gerber, Robert A.; Liegl, Bernhard; Knorr, A.; Economikos, Laertis; Simpson, A.; Yan, Wendy; Dobuzinsky, D.; Mandelman, J.; Nesbit, L.; Radens, C.; Divakaruni, R.; Bergner, W.; Bronner, G.; Mueller, Wolfgang

doi:10.1109/iedm.2001.979525

Cited by 7 publications

(3 citation statements)

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“…Devices were fabricated using a DRAM process flow similar to the one reported in [5]. A low-energy BF implant is used to create the shallow PMOS buried-channel layer.…”

Section: Singlework Function Transistor Fabricationmentioning

confidence: 99%

“…Gate SWox is required for planar DRAM cells to reduce the electric field around the gate wordline-storage node overlap region to improve cell-retention time characteristics. However, in a vertical-cell DRAM, the wordline-storage node region is buried [5] and consequently, gate SWox has no impact on cell-retention characteristics. To take full advantage of the novel features of a vertical-cell DRAM, transistors reported in this letter do not have gate SWox.…”

Section: Introductionmentioning

confidence: 99%

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1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

Rengarajan

He²,

Ransom³

et al. 2002

IEEE Electron Device Lett.

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This letter reports on 1.5-V single work-function W/WN/n + -poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At of 1.5-V and 25 C, drive currents of 634 A/ m for 90-nm gate NMOS and 208 A-m for 110-nm gate buried-channel PMOS are achieved at 25 pA/ m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.

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“…Devices were fabricated using a DRAM process flow similar to the one reported in [5]. A low-energy BF implant is used to create the shallow PMOS buried-channel layer.…”

Section: Singlework Function Transistor Fabricationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

Rengarajan

He²,

Ransom³

et al. 2002

IEEE Electron Device Lett.

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“…Such a new DRAM cell concept is the Vertical Transistor Cell design [1]. Within this concept a new type of layer is needed to isolate the capacitor from the active transistor area.…”

Section: Introductionmentioning

confidence: 99%

Simulation and Design of an HDP-CVD Process for Planar Spacer Applications for Future DRAM Cell Concepts

Weber

Radecker

Schulze-Icking-Konert

et al.

The 17th Annual SEMI/IEEE ASMC 2006 Conference

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High Density Plasma Chemical Vapor Deposition is a well known process for gap-fill applications. This paper describes the usage of High Density Plasma Chemical Vapor Deposition to generate a buried isolation layer (Planar Spacer). A study to meet Planar Spacer requirements is presented based on simulations on reactor and feature scale. It explains variations from wafer center towards the edge in within-trench fill height uniformity, sidewall coverage and hat height. Plasma density variations across the wafer surface and subsequently deviations of incoming ions off the normal direction were found as the main contributor. Simulation results could be confirmed by several experiments. Based on this results a new type of High Density Plasma Chemical VaporDeposition process was designed to achieve homogenous within trench fill heights and pattern across the wafer and is therefore suitable for Planar Spacer applications.

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Highly scalable sub-50nm vertical double gate trench DRAM cell

Schloesser

Manger

Weis

et al.

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.

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A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond

Cited by 7 publications

References 0 publications

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

Simulation and Design of an HDP-CVD Process for Planar Spacer Applications for Future DRAM Cell Concepts

Highly scalable sub-50nm vertical double gate trench DRAM cell

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