A holistic methodology for network processor design

Abstract

The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, evaluation, and realization of a parameterizable network processing unit. In this paper we present a design methodology for network processors which encompasses the research areas from the application software down to the gate level of the chip. Key components of this holistic approach have been successfully applied to characteristic examples of architecture refinements.

Analytical approach to massively parallel architectures for nanotechnologies

“…In this section we describe an exemplary implementation of a chip multiprocessor, the GigaNetIC architecture [3] [20]. We then analyze this architecture with regard to the presented metrics discussed in section 2.…”

“…As decreasing structure sizes are considered this total area is to be kept constant as in general chip sizes stay fairly constant over the course of technological generations. Table 2 lists the values of the parameters of the BSP-based model according to the specifications of the GigaNetIC (see [3][19] [5][11] [7]). As described in section 2.4 these values suffice to calculate the BSP parameters for the GigaNetIC CMP in various structure sizes and get a good idea of its performance as a BSP computer.…”

“…Each core having access to low latency on-chip memory and connected to the other cores by a powerful communications system, the chip is essentially a small scale parallel computer. This basic idea is not new (see [22]) and a number of research groups have already developed examples of such architectures (see [13][2] [28] [3]). The analysis of the underlying concept however has mostly been done by simulation (see [22][15] [21]), which is a very laborious and costly process.…”