Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003
DOI: 10.1145/764808.764828
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A hybrid adiabatic content addressable memory for ultra low-power applications

Aiyappan Natarajan
1
,
David Jasinski
2
,
Wayne Burleson
3
et al.
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Cited by 11 publications
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References 6 publications
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Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories

Mahoney
1
,
Savaria
2
,
Bois
3
et al. 2009
Transactions on High-Performance Embedded Architectures and Compilers II
2
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1
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Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories

Mahoney
1
,
Savaria
2
,
Bois
3
et al. 2009
Transactions on High-Performance Embedded Architectures and Compilers II
2
0
1
0
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Design of a Two-Phase Adiabatic Content-Addressable Memory

Chang
1
,
Kuo
2
2011
Lecture Notes in Electrical Engineering
1
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0
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Design and Implementation CAM Architecture Memory Cell Using DMLSA Technique

Rao
1
,
Kumar
2
,
Raghavendra
3
et al. 2011
Trends in Network and Communications
1
0
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