A hybrid wave pipelined network router

48th Midwest Symposium on Circuits and Systems, 2005.

2005

Self Cite

Abstract-Pipelining digital systems has been shown to provide significant performance gains over non-pipelined systems and remains a standard in microprocessor design. The desire for increased performance has seen a push for deeper pipelines, as well as the introduction of pipelining schemes such as wavepipelining and hybrid wave-pipelining. In this paper we present a hybrid wave-pipelined parallel adder that operates at 1.79 GHz, ¾± performance improvement compared to that of a superpipelined adder. The simulations have been performed using a modest 0.25 m technology. The three stage hybrid wavepipelined parallel adder sustains a total of 8 unrelated data waves within the pipe. Another performance benefit achieved by using the the hybrid wave-pipelining scheme is the lessening of delays associated with clock skew and clock distribution.

Section: Pipelining Schemesmentioning

confidence: 99%

High-performance parallel addition using hybrid wave-pipelining

Levy

Nyathi

48th Midwest Symposium on Circuits and Systems, 2005.

2005

Self Cite

“…The clock period T clk of this system is determined by stage with the largest delay difference and safe time required before a new data wave is admitted into this stage [3]. The fundamental circuit limitations determine the safe time to separate any two adjacent data waves.…”

Section: Figure 1 Hybrid Wave-pipelining Schemementioning

confidence: 99%

A High Performance Hybrid Wave-Pipelined Multiplier

Tatapudi

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

Self Cite

The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8×8-bit hybrid wave-pipeline multiplier using carry-save adder technique is described. The multiplier has been designed using TSMC 180nm. The basic cells in multiplier are designed to have small propagation delay and delay variation. The hybrid wave-pipelined multiplier is able to achieve 2.86 billion multiplications per second.

“…Figure 2-6 shows a temporal/spatial representation of the data waves in a wave-pipelining system [7]. The data path delays, setup and hold time of the output latch, and clock skew affect the minimum spacing possible in the waves.…”

Section: Wave-pipeliningmentioning

confidence: 99%

“…This allows for the data waves present in the system to be compressed further, since the system is now dependant upon the difference in path delays per stage instead of in the whole pipeline [7].…”

Section: Introductionmentioning

confidence: 99%

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

Nyathi

2003 46th Midwest Symposium on Circuits and Systems

Self Cite

Chair: Jabulani Nyathi Clock skew and clock distribution are increasingly becoming a major design concern in high performance, high density synchronous systems. Large clock networks are required for efficient clock distribution and they contribute significantly to the power dissipated by the system, while clock skew takes up a considerable percentage of the clock period.Design effort for clock networks is currently estimated to take up 20% of system design time, while power dissipation due to the clock network is reported to be 30% of the total dissipation. It is therefore necessary to investigate the possibilities of other schemes that could results in cost reduction by avoiding complicated architectures while facilitating fast logic.We explore the possibility of managing clock skew and reducing clock loading by applying the hybrid wave-pipelining scheme to a linear feedback shift register. The hybrid wave-pipelining scheme takes advantage of interconnects and data path delays to optimize clock skew and allows the clock to "travel" with its associated data. The system's clock in conjunction with stage delays is used to generate wave-pipelined clocks that have short cycle times and are skew tolerant. The hybrid wave-pipelined clock is designed to mimic the data path elements of the LFSR stage, thus reducing the uncontrolled clock skew, as well as clock loading. Thus, the iv resulting skew is a result of the data path circuitry. A LFSR would provide a good means of measuring clock skew since the common edge of the clock triggers data transfer.Linear feedback shift registers also have numerous common uses including pseudorandom number generator, random pattern generator and analyzer, encryption/decryption and direct sequence spread spectrum for digital signal processing. Their study with different clocking schemes is beneficial as LFSRs are easy to analyze and are found in many applications as mentioned.In this thesis, it is shown that the use of hybrid wave-pipelining provides significant clock skew improvements (six times) compared with a buffered clock design, and also offers improved clock cycle time. There is also potential for a reduction in power dissipation associated with the clock trees, since the scheme reduces the need for complicated clock distribution networks.