A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces

Kim, Hyun‐Jin; Abraham, Jacob A.

doi:10.1109/ats.2010.30

Cited by 3 publications

(4 citation statements)

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“…However, as data rates are increasing, controlling the patterns at every clock cycle become challenging. Therefore, this paper extends the previous work [11] to increase the test accuracy by resolving frequency limitations of internal control circuits such that it can be used to test higher speed memory interfaces. We use a phase interpolator to generate and control precise time delays.…”

Section: Introductionmentioning

confidence: 70%

“…The signal generator generates signal patterns of DQ n , DQS, CLK and HCLK. The coarse and fine control units control the time delay between the generated pattern and the test clock using a cycle-by-cycle method [11]. This method increases or decreases the time delay by an amount determined by the resolution of the fine control unit at every clock cycle.…”

Section: A Architecturementioning

confidence: 99%

“…A phase interpolator is used in the fine control circuit to generate a small delay and a test method for finding its resolution is also presented. We use the signal generator and control circuits presented in [11]. Furthermore, we add dividers to resolve internal signal integrity.…”

Section: A Architecturementioning

confidence: 99%

“…However, these methods need an external high frequency clock and thus are not compatible with low cost testers. In [11], a low cost BIST method was presented to test DDR I/O timing parameters. This method generates a relative time delay between data and clock, which does not require any external clock.…”

Section: Introductionmentioning

confidence: 99%

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A Built-In Self-Test scheme for DDR memory output timing test and measurement

Kim

Abraham

2012

2012 IEEE 30th VLSI Test Symposium (VTS)

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This paper presents a Built-In Self-Test (BIST) scheme to measure high speed double data rate (DDR) memory output timing using low cost testers. This technique uses an onchip pattern generator to generate a time delay between data and data-strobe or clock. The time delay is controlled precisely using a phase interpolator based cycle-by-cycle control method. A novel method for testing the resolution of phase interpolator, which does not need any extra hardware, is also presented. Using the test resolution, a timing pass/fail flag is set and the timing margin is quantified as a multiple of the test clock cycle. Since these test results have high observability, output per-pin timing performance can be diagnosed easily, which is especially good for testing parallel memory interfaces. Moreover, these features make our scheme compatible with low-cost testers and decreases the time-to-market for the chip. The BIST circuit has been implemented using the 0.18-µm CMOS process, and chip measurement results are presented. We obtained a test resolution of 10 ps for testing output timing. Using the fabricated test chip, this paper shows the effects of switching noise, per-pin skews and slew-rate change on output timing variations.

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Section: Introductionmentioning

confidence: 70%

Section: A Architecturementioning

confidence: 99%

Section: A Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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