A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test

Chen, Tao; Park, Chulhyun; Meng, Hao; Zhou, Dadian; Silva-Martí­nez, J.; Geiger, R.L.; Chen, Degang

doi:10.1109/tim.2019.2936716

Cited by 16 publications

(22 citation statements)

References 20 publications

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“…Recently, DACs with low power consumption and small die area have become a topic of interest especially in portable devices (Yi, 2012; Sharifi et al , 2016). Small size DAC is very important for ADC built-in self-test (Chen et al , 2020). Nonetheless, low power DAC design normally comes with tradeoff between speed and precision (Wang et al , 2018).…”

Section: Introductionmentioning

confidence: 99%

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

Idros

Rosli

Aziz

et al. 2021

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Purpose The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures. Design/methodology/approach The conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V. Findings Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm2 DAC consumed 12.6 mW for the data conversion. Originality/value This paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.

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Section: Introductionmentioning

confidence: 99%

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

Idros

Rosli

Aziz

et al. 2021

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show abstract

“…In [7], a 14-bit subradix-2 R2R DAC BIST with a constant voltage shift generation capability was developed to implement the USER-SMILE algorithm. The subradix-2 R2R DAC architecture was chosen as it can be easily built for a high resolution without high area requirement, and with the radix designed to always produce a negative DNL at major transitions, large positive jumps in DAC output are avoided which is a requirement of the USER-SMILE algorithm [7]. The constant voltage shift is implemented by adding a shift resistor to the R2R structure.…”

Section: User-smile Bist Solutionmentioning

confidence: 99%

“…This thesis reviews the design proposed in [7], identifies an area of improvement, and proposes a more optimized sizing strategy that reduces the error in USER-SMILE algorithm by improving shift constancy of the subradix-2 R2R DAC structure by a factor of 2.…”

Section: User-smile Bist Solutionmentioning

confidence: 99%

“…First, the autocorrelation of site 0 f f ★ is calculated for that parameter. Then cross-correlation f g ★ is calculated and a score is assigned to subject site based on equation (7).…”

Section: Cross-correlation (Cc)mentioning

confidence: 99%

“…The USER-SMILE algorithm relaxes the stringent signal generator linearity requirement and reduces the required number of samples per code [6]. In [7], a 14-bit subradix-2 R2R DAC BIST was developed to implement the USER-SMILE algorithm. The design was analyzed and an area for improvement was identified.…”

Section: Introductionmentioning

confidence: 99%

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Reducing integrated circuit test cost through improvements in multisite testing and built-in self-test

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In-field Built-in Self-Test for Detecting Incipient Faults in Analog Reconfigurable Filters

Vélez Ibarra,

Vodanovic,

Laprovitta

et al. 2024

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A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test

Cited by 16 publications

References 20 publications

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

Reducing integrated circuit test cost through improvements in multisite testing and built-in self-test

In-field Built-in Self-Test for Detecting Incipient Faults in Analog Reconfigurable Filters

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