A Low-Cost Tiny-Size Successive Approximation ADC for Applications Requiring Low-Resolution Conversion with Moderate Sampling Rate

Aminzadeh, Hamed

doi:10.1007/s00034-018-0854-0

Cited by 8 publications

(4 citation statements)

References 23 publications

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“…Te preamplifer stage, single-stage dynamic latch, and bufer stage are integrated in the SAR comparator [1,31,103] to decrease the delay, power consumption, kick-back noise, and the inputreferred ofset voltage. Also, two inverter stages may be used with the single-stage dynamic latch [29,52,58] to avoid the static current at the reset phase and to enhance the driving capability and achieve rail-to-rail digital output. Based on the dual sampling technique as mentioned in Section 5, a four-input dynamic comparator is utilized in [58].…”

Section: Tree-stage Dynamic Latchmentioning

confidence: 99%

“…Tis technique achieves higher energy saving and less area as compared with the conventional technique. In addition, the linearity is enhanced and the parasitic capacitor efect is eliminated [27][28][29][30].…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…Meanwhile, to decrease the die size, cost, and the threshold voltage, the MIM (metal-isolated-metal) capacitor DAC array is replaced by a MOS capacitor [29]. Also, a modifed two-stage dual split CDAC array technique is used to avoid the mismatch ofset and reduce the capacitor array size [31][32][33][34].…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…Two diferent implementations of SAR register and its logic control are used, including the sequence/code register and nonredundant SAR logic [92]. Te sequence/ code register [10,11,29,33,92,102,103] shown in Figure 36 is divided into two groups of registers. A set of sequence registers is arranged as a ring counter to determine the output bits.…”

Section: Sar Register and Its Control Logicmentioning

confidence: 99%

See 3 more Smart Citations

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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