A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

Liang, Yuan; Boon, Chirn Chye; Qi, Gengzhen; Dziallas, Giannino; Kissinger, Dietmar; Ng, Herman Jalli; Mak, Pui-In; Wang, Yong

doi:10.1109/tmtt.2022.3156901

Cited by 23 publications

(5 citation statements)

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“…As described by the above, frequency tuning capability of the signal source is also important to allow both phase and frequency locking to an external low noise reference source. As shown in Figure 17A, PLLs operating from 300 to 560 GHz were reported in silicon process 69–71 . The die micrograph and measured phase noise are provided in Figure 17B,C, respectively.…”

Section: Thz Signal Sources With Power Combiningmentioning

confidence: 99%

“…As shown in Figure 17A, PLLs operating from 300 to 560 GHz were reported in silicon process. [69][70][71] The die micrograph and measured phase noise are provided in Figure 17B,C, respectively. These results are highly potential to serve as a local source generator for large-scale arrays for imagers and transmitters.…”

Section: Adnan Andmentioning

confidence: 99%

“…With approaches utilizing photo-mixer, photonic approaches of continuous THz-wave generation have been improved as well, showing several tens of μW of output power 68 and a power level reaching up to milliwatt (mW) in the 1-2 THz range by utilizing nonlinear materials. 60 Moreover, fully integrated silicon integer-N frequency synthesizers have demonstrated the highest locking frequency beyond 0.3 THz, [69][70][71] with 122 fs rms integrated jitter and $À3 dBm output power without power combining. As required by fast programmability, practical THz systems have to fulfill highoutput-power generation (for transmitter) and high-sensitivity detection (for receiver).…”

Section: Introductionmentioning

confidence: 99%

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Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

Shan

Liang

Li³

et al. 2023

Circuit Theory & Apps

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SummaryThe research and development on solid‐state source generators have been making progress on chip, aiming to generate low noise, high output power, and high DC‐to‐RF energy efficiency in the millimeter‐wave (mmW) and terahertz (THz) domains. In particular, their full integration in silicon technologies, such as advanced complementary‐metal‐oxide‐semiconductor processes, has motivated the design of low cost, high performance, and miniature integrated circuits (ICs). This manuscript focuses on providing a general overview of recent progress on solid‐state signal source operating beyond 60 GHz till the THz region, from the perspective of operating principle, design metrics, state‐of‐the‐art performance, testing results, and their applications in emerging mmW/THz systems. Finally, with the use of fully integrated source generators, several design arts are highlighted to showcase the recent advances of ICs toward millimeter‐wave and THz radiation, imaging, coupled oscillator network (CON), and communication. Potential future research directions enabled by mmW/THz signal sources will be envisioned.

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Section: Thz Signal Sources With Power Combiningmentioning

confidence: 99%

Section: Adnan Andmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

Shan

Liang

Li³

et al. 2023

Circuit Theory & Apps

Self Cite

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“…technology is generating and capturing a wealth of data that was previously unimaginable.New social media with web-logs and images on Facebook would now generate Exa-scale data.International Data Corporation (IDC-USA) predicts that big data and analytics solutions has reach 215.7B-USD market in 2021[1]. However, the scale of growing data has gone beyond the scale of Moore's law that governs the data-processing capability of data servers.…”

mentioning

confidence: 99%

“…Moreover, the shrinking of power consumption has slowed down from 40-nm node to 7-nm node. In fact, many recent research programs such as Exa-scale Computing and Human Brain are trying to address this scalability issue: can we scale down data center on chip as a personalized cloud server, like the human brain[1]-[4], with low cost and low power?…”

mentioning

confidence: 99%

Siliconization of millimeter-wave to terahertz surface-plasmonic transceiver and phase-locked loops

Liu¹

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The future 6G network and big-data center will be generating and capturing a wealth of data that was previously unimaginable. The conventional inter-server interconnects rely on optical cables that can reach Tera-scale; however, they are not fully based on integrated circuit (IC) processes and hence cannot be scaled down for both cost and power. Full integration in the complementary metal-oxidesemiconductor (CMOS) technologies has been identified as the ultimate solution to build the low-cost, low-power, highly compact interconnect that meets the stringent requirement of next generation 100/400 GbE communication. Unfortunately, silicon channels suffer from strong electromagnetic crosstalk (and loss) at high speed with limited output power generated by the signal source. To overcome such issues, conventional data interfaces have implemented crosstalk-compensated equalizers and signal source leading to an excessively high 5-20 pJ/bit power efficiency. Furthermore, crosstalk-compensated equalizers have limited speeds up to 13 Gb/s.Recently, the integrated surface plasmonic polaritons (SPPs) components and circuits were proposed and implemented in silicon at the ultra-broadband terahertz (THz) frequency toward high-speed, lowpower, low-crosstalk signaling. The surface plasma (or surface wave) is a special electromagnetic (EM) wave to localize the free electron into the metal/medium interface, achieving extraordinary field confinement and enhancement. Implemented in advanced CMOS technologies, the design will be smaller, lighter, cheaper, and scalable for emerging applications such as low-crosstalk digital signaling, ultrahigh-speed communication, low-power transceiver, remote sensing, and threat detection.As there is a lack of knowledge on how to achieve surface plasmonic generation, transmission, modulation, conversion, and amplification in silicon, this thesis aims to conceptualize, design, implement, and validate several on-chip high-performance metadevices. Several I/O interface architectures are reviewed in Chapter 2, followed by the introduction of SPPs fundamentals, design, and comparison to conventional on-chip transmission lines. The impact of channel crosstalk on bit-error rate (BER) as well as power consumption will be evaluated based on link budget analysis. To evaluate how plasmonic can attenuate the channel crosstalk, the surface wave transmission lines (T-line) are modeled on the T-section network incorporated by the lossy T-line model. This model can also describe the impedance, phase shift, dispersion behavior, and loss of the surface plasmonic T-line from the circuit's perspective. Like other surface plasmonic T-lines implemented on the printed circuit boards (PCBs), impedance or momentum mismatch occurs between the TEM devices and the plasmonic devices. A gradient groove plasmonic converter is designed and experimentally verified in Chapter 3. Since the coplanar waveguide (CPW) is not involved for impedance conversion, the design is compact and therefore suitable for on-chip implementation.A split-...

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Terahertz metadevices for silicon plasmonics

Liang¹,

Yu²,

Wang³

et al. 2022

Chip

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A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

Cited by 23 publications

References 38 publications

Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

Siliconization of millimeter-wave to terahertz surface-plasmonic transceiver and phase-locked loops

Terahertz metadevices for silicon plasmonics

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