A Low Loss Power Distribution Network Design in Low Temperature Co-fired Ceramic Technology

Abstract

The development of power distribution networks in low temperature co-fired ceramic (LTCC) to deliver power to electronic chips with minimal power loss and/or voltage drop presents real challenges. In the last decade, the power consumption for some applications has increased considerably while the supply voltage has been reduced. A number of designs for low loss power distribution networks were investigated for implementation using low temperature co-fired ceramics (LTCC) technology. This paper discusses the fabrication of power distribution networks (PDNs) using LTCC technology that exhibit sub-milliohm resistance through the use of full tape thickness features and other structures. Experimental data is also presented to support the viability of the approaches presented. The results presented in this paper show that the finite DC conductivity of the silver conductor paste commonly used in LTCC fabrication presents a challenge when attempting to build PDNs with low losses at high current levels. By analyzing a number of scenarios, several approaches are proposed that reduce the DC resistance laterally as well as vertically in a multi-layered LTCC PDN. Experiments and simulations show that the use of various processing techniques to increase the thickness of metallic traces can significantly reduce the lateral DC resistance of the PDN structure. In addition, various via configurations were simulated and fabricated that demonstrate an improvement in the performance of structures that distribute power vertically. Experiments using LTCC to carry a 100 A current were conducted to confirm simulations.