A Low Phase Noise Class-C Oscillator With Improved Resonator and Robust Start-Up

Sheikhahmadi, Saman; Moezzi, Mohsen; Ghafoorifard, Hassan

doi:10.1109/tcsii.2020.3005251

Cited by 5 publications

(5 citation statements)

References 11 publications

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“…To reduce phase noise in cross-coupled oscillators, many research efforts have been carried out in recent years, each of which has distinct advantages and disadvantages. In an earlier study, by improving the resonator's design, the researchers also attempted to reduce phase noise as discussed in [12][13][14]. In [10], an active resonator with a high Q factor was used to minimize phase noise.…”

Section: Literature Review Commonly Used Techniques In Traditional Lo...mentioning

confidence: 99%

“…In [10], an active resonator with a high Q factor was used to minimize phase noise. In [13,14], the study's findings were that the oscillator's phase noise efficiency can be enhanced by increasing the inductance energy factor (IEF). In [15], the tail current shaping technique was used to manage tail current and improve phase disturbance.…”

Section: Literature Review Commonly Used Techniques In Traditional Lo...mentioning

confidence: 99%

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Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Siddiqui,

Maheshwari,

Raza

et al. 2023

JLPEA

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This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

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Section: Literature Review Commonly Used Techniques In Traditional Lo...mentioning

confidence: 99%

Section: Literature Review Commonly Used Techniques In Traditional Lo...mentioning

confidence: 99%

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Siddiqui,

Maheshwari,

Raza

et al. 2023

JLPEA

View full text Add to dashboard Cite

show abstract

“…In Park et al, 17 for example, phase noise was improved by increasing the Q of the tank circuit and inducing negative resistance through transistors. In previous studies, [22][23][24] the researchers also attempted to reduce phase noise by improving the structure of the resonator. In Vincenzo et al, 22 phase noise was reduced by using an active resonator with high Q factor.…”

Section: Studies On Lc Oscillatorsmentioning

confidence: 99%

“…In Vincenzo et al, 22 phase noise was reduced by using an active resonator with high Q factor. The authors explained in Moezzi and Bakhtiar and Sheikhahmadi et al 23,24 that increasing the inductance energy factor (IEF) can improve the phase noise performance of the oscillator. In Soltanian and Kinget, 18 phase noise was enhanced by controlling tail current via tail current shaping.…”

Section: Studies On Lc Oscillatorsmentioning

confidence: 99%

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

Kebria

Ghonoodi

2020

Circuit Theory & Apps

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SummaryThis study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to −123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to −193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.

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“…There have been several works on improving FoM through decreasing phase noise or power consumption in cross-coupled oscillators [2], [3], [4], [5]. For instance some methods like current reuse [6], incorporating a new resonator [7], using Darlington structure [8] and making the tail current source to work in sub-threshold region [9] can be used to lower the phase noise and thus improving the FoM. [10] optimized the sizing of the transistors to maximize the FoM.…”

Section: Introductionmentioning

confidence: 99%

FoM Optimization in Class-C Oscillators

2023

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In this paper, a new approach to optimize phase noise and Figure-of-Merit (FoM) in class-C oscillators is presented. This approach recruits DC voltage of the common source node of the switching pair transistors as an indicator to achieve the best performance of a class-C oscillator. The proposed indicator has the advantages of not introducing any loading effect to the output node, and independency from PVT changes. The method is simple and applicable to any oscillator with class-C topology, and with some modifications it would be applied to other oscillator topologies like class-B. The idea is verified using theoretical analysis, and circuit simulations on 0.18µm CMOS technology at 2GHz oscillation frequency. Moreover, a discrete prototype is fabricated at 15MHz and measurement results are provided which further validate feasibility of this approach.

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A Low Phase Noise Class-C Oscillator With Improved Resonator and Robust Start-Up

Cited by 5 publications

References 11 publications

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

FoM Optimization in Class-C Oscillators

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