A Low Power 90 nm LNA with an Optimized Spiral Inductor Model for WiMax Front End

Abstract

The capability of 90 nm CMOS technology for low-power RF front-ends is demonstrated using fully integrated low power low noise amplifiers. This paper presents a 5.25 GHz high linearity, high gain LNA design for a receiver architecture based on IEEE802.16a WMAN standard. First, we go through the standard in order to obtain the receiver specifications. Next we choose a suitable architecture for our receiver and simulate it using ADS cad tool to extract the specifications which are needed for the low noise amplifier. Finally we design our LNA based on the design method of Mr. D. K. Shaefer, also we improve the Greenhouse spiral inductor model and optimize it employing a random search algorithm named Simulated Annealing. The targeted frequency band is the unlicensed band UNII 5 GHz. The LNA achieves voltage gain of 24 dB, noise figure of 1.8 dB, the TIP3 of 7.5 dBm, and the reverse isolation is about -11. 6. Employing the 90 nm CMOS process, the LNA dissipates 1.75 mW using a 1.2 V supply voltage.

Comparison of LNA Topologies for WiMAX Applications in a Standard 90-nm CMOS Process

“…The cascode transistor M2 suppresses the Miller capacitance of M1 thereby increasing the reverse isolation [6]. The suppression of the parasitic capacitances of the input transistor also improves the high frequency operation of the amplifier.…”

Nanoscale RF CMOS transceiver design

“…The input impedance is purely resistive only at ω 0 , hence the method can provide a narrow-band impedance match. The circuit topology is called inductively degenerated cascode LNA (Figure 2.6), and can be found in numerous publications [29][30][31][32][33][34][35][36][37][38][39][40][41][42], due to its simplicity and high performance, compared to standard CG and CS topologies. The one and only current path makes the topology ideal for low-power applications, as will be shown in Chapter 4.…”