A low-power analog sampled-data VLSI architecture for equalization and FDTS/DF detection

Carley, I.R.; Bracken, K.C.; Mittal, Ratik; Park, J.

doi:10.1109/20.364807

Cited by 11 publications

(4 citation statements)

References 11 publications

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“…A logic output of one corresponds to NRZ , and a logic value of zero for is interpreted as NRZ . Similar structures for were presented in [20] and [21]. In terms of hardware, the max-finder circuit is replaced by singlebit quantizers (slicers) and a combinational logic circuit.…”

Section: The Signal Space Detector (Ssd)mentioning

confidence: 91%

“…A particular class of signal space detectors exist that mimic the performance of FDTS using linear boundaries [20]. This approach that was taken to develop detectors for RLL channels [10]- [12], [21] as well as enhanced DFE [22]. In FDTS the distances from the received symbol and the noiseless points are computed, and the smallest one (maximum for negative distances) is chosen as the winner.…”

Section: The Signal Space Detector (Ssd)mentioning

confidence: 99%

“…The boundary between and is the locus of points equidistant from the two symbols; i.e., (19) This boundary is realized with an finite impulse response (FIR) filter and an offset term as (20) where is 1 for closest to and 1 for closest to . The boundary terms are given by (21) and (22) The terms in (21) and (22) are scaled so that . This step is justified because the magnitude is not important.…”

Section: The Signal Space Detector (Ssd)mentioning

confidence: 99%

See 2 more Smart Citations

Architectures for the implementation of a fixed delay tree search detector

Brickner

Moon²

1997

IEEE Trans. Magn.

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This paper examines the tradeoff between fixed delay tree search (FDTS) detector complexity and performance with various modulation codes. Several architectures suitable for implementing FDTS or achieving performance comparable to FDTS are presented. Recursive forms are derived by decomposing the branch metric computation while breaking down the entire path metric yields nonrecursive forms. The final architecture casts the detection problem into a signal space context in which the observation space is partitioned into decision regions. These structures are presented and evaluated in the context of an analog very large scale integration (VLSI) implementation. Compared to a direct mapping to hardware of the original algorithm, these alternative schemes offer reduced power consumption and/or increased data rate.Index Terms-Decision feedback equalizers, digital magnetic recording, fixed delay tree search, multidimensional signal detection, sampled data systems, signal detections.

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Section: The Signal Space Detector (Ssd)mentioning

confidence: 91%

Section: The Signal Space Detector (Ssd)mentioning

confidence: 99%

Section: The Signal Space Detector (Ssd)mentioning

confidence: 99%

See 1 more Smart Citation

Architectures for the implementation of a fixed delay tree search detector

Brickner

Moon²

1997

IEEE Trans. Magn.

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“…Also, the multi-level decision feedback equalizer (DFE) was derived using a geometrical representation for FDTSIDF of depth 1 with d=1 coded data [10], [11], [12]. A practical method for analog implementation of FDTS/DF with r= 1 based on this geometrical interpretation has been developed [13].…”

Section: Introductionmentioning

confidence: 99%

A signal space representation of fixed delay tree search for use with d=0 codes

Brickner

Moon

Proceedings of GLOBECOM '95

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This paper addresses the optimality of the fixed delay tree search with decision feedback (FDTSIDF) detector for data without a minimum run length constraint. The evaluation is performed by comparing the minimum distance for FDTSIDF with the minimum distance associated with a maximum likelihood sequence detector (MLSD). Using this distance information, potential improvements through coding areaddressed.An alternative realization to the direct implementation of FDTS/DF is considered by examining the detection process in the context of a signal space.

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Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 μm Technology

Długosz

Iniewski²

2008

J Sign Process Syst Sign Image Video Technol

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This paper presents a programmable multi-mode finite impulse response (FIR) filter implemented as switched capacitor (SC) technique in CMOS 0.18 μm technology. Intended application of the described circuit is in analog base-band filtering in GSM/WCDMA systems. The proposed filter features a regular structure that allows for elimination of some parasitic capacitances, thus significantly improving the filtering accuracy. Due to its modularity that allows for dividing the circuit into two separate sections, the circuit can be easily reconfigured to work as either infinite impulse response (IIR) or as finite impulse (FIR) filter. One of the key components that allows for this multi-mode operation is the proposed programmable and ultra low power multiphase clock circuit. The 24-taps filter for the sampling frequency of 30 MHz dissipates power of 4.5 mW from a 1.8 V supply.

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A low-power analog sampled-data VLSI architecture for equalization and FDTS/DF detection

Cited by 11 publications

References 11 publications

Architectures for the implementation of a fixed delay tree search detector

Architectures for the implementation of a fixed delay tree search detector

A signal space representation of fixed delay tree search for use with d=0 codes

Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 μm Technology

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