A low power and high picture quality H.264/MPEG-4 video codec IP for HD mobile applications

An Overview of H.264 Hardware Encoder Architectures Including Low-Power Features

“…For example, the rate control scheme requires the amount of entropy encoded data to choose the appropriate mode. Data dependency among tasks can be solved by the use of new rate control schemes [16,17]. Other work placed the reconstruction task across the last two stages [9,18].…”

“…Others used specific low-power techniques, e.g. power gating and clock gating [9,15,16]. Moreover, the encoder might be reconfigurable to change its profile/features so as to adapt with the power consumption requirements [9,17].…”

“…With fewer logic gates and less processing time, this solution avoids limiting number of mode candidates while keeping high picture quality. With a faster Intra stage, the design in [16] is slightly less balanced than the one in [8]. Most of its improvement is provided by its special techniques, but not by the architecture.…”

“…To support video-size scalability, on-chip connections DCSS [16] and fine-grained clock gating [9] exploit schedule of H.264 encoder.…”

“…Among these techniques, DCSS [16] and fine-grained clock-gating [9] exploit the inactive state of sub-modules to reduce their idle power consumptions. Figure 4 shows the schedule of modules in an H.264 encoder and the time slots when power can be saved.…”