A Low Power Block-Matching Analog Motion Estimation Processor

Panovic, M.; Demosthenous, Andreas

doi:10.1109/iscas.2005.1465713

Cited by 7 publications

(2 citation statements)

References 8 publications

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“…Various Block Matching algorithms were proposed so far to reduce complexity involved in ME, among all those algorithms Full Search [5] algorithm approaches best PSNR as it searches for every possible block within the search window(32x32,48x48). but it involves higher computational complexity.…”

Section: Introductionmentioning

confidence: 99%

New fast search block matching Motion Estimation algorithm for H.264 /AVC

Reddy

Muralidhar

Rao

2014

2014 International Conference on Recent Trends in Information Technology

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Video encoding algorithms with less complexity are required in many real time video coding applications. Motion Estimation (ME) is computationally intensive part of video compression. This paper introduces One bit transformation ME algorithm, which transforms the video sequences from multi-bit to a single bit per pixel representation and then used conventional motion estimation search strategies, this will reduce the arithmetic calculations and hardware complexity while maintaining almost good compression performance. In this paper, we propose an efficient fast search ME method for one bit transform to reduce computations involved in determining motion of blocks in a frame. The proposed Fast search algorithm effectively estimates the motion information in video. Experimental results shows 50% reduction in computations with a marginal loss of 3% PSNR compared to the conventional Exhaustive search algorithm.

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Section: Introductionmentioning

confidence: 99%

New fast search block matching Motion Estimation algorithm for H.264 /AVC

Reddy

Muralidhar

Rao

2014

2014 International Conference on Recent Trends in Information Technology

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“…Among these algorithms, Full Search (FS) is that present the best quality results at the cost of an increased computational complexity. Thus, some of the works presented in literature aim to reduce the computational complexity of the FS algorithm [4]. However, due to the complexity of the FS algorithm, some other works have proposed the use of less complex algorithms, so that quality results close to the FS algorithm can be kept.…”

Section: Introductionmentioning

confidence: 99%

A real time and power efficient HDTV motion estimation architecture using adder-compressors

Porto

Bampi

Altermann

et al. 2011

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS)

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This paper presents a high performance and power efficient architecture for motion estimation (ME). For this architecture two algorithms are implemented, a Sub-sampled Diamond Search (SDS) and a Quarter Sub-sampled Diamond Search (QSDS), both with Dynamic Iteration Control (DIC) algorithm. The SDS-DIC and QSDS-DIC algorithms can significantly reduce the number of SAD (Sum of Absolute Difference) calculations enabling the development of an efficient hardware design for the ME. The DIC technique allows that the desired throughput can be achievable with a restriction in the number of iterations, which contributes for the reduction of number of clock cycles for the motion vector calculation. The processing units (PU) of the ME were developed by using efficient 4-2 and 8-2 adder-compressors. The results we present show that by using both the adder compressors in the PU and the DIC technique it is possible to obtain an efficient ME architecture with a higher performance and a reduced power consumption. The implemented architecture was described in VHDL. Synthesis results are presented for TSMC 0.18um CMOS standard cell. The architecture can reach real time for HDTV 1080p with power consumptions lower than 33mW.

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