A low-power single-ended SRAM in FinFET technology

Ensan, Sina Sayyah; Moaiyeri, Mohammad Hossein; Moghaddam, Majid; Hessabi, Shaahin

doi:10.1016/j.aeue.2018.12.015

Cited by 69 publications

(16 citation statements)

References 23 publications

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“…Here for evaluation purposes the selected cell is considered to be undergoing write operation and the control signals are assigned in keeping with signal status in table 3. Ideally, the HS cells are not a part of the on-going operation, but due to common control signal for row or column, they get partially selected [62]. The SNM curve for the half selected cells is depicted in figure 10 b and 10 c .…”

Section: Half Select Disturbance and Soft Error Resiliencementioning

confidence: 99%

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

Rawat

Mittal

2022

Proc. R. Soc. A.

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In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access memory bit cell is presented. The cell is designed based on a detailed review of various pre-existing 7T cells. All the cells in the paper are evaluated at 32 nm technology and supply voltage of 0.8 V. The static analysis reveals that the hold/read noise margins for the proposed cell are 324 mV each, whereas the write margin is 488 mV. Successful read and write operation for the cell requires a pulse-width of 5 ps and 0.14 ns, respectively. The temperature variation and process corner analysis are used to justify the reliability for the proposed cell. The former analysis yields 0.15 and 0.24 mV/°C variation in the HSNM/RSNM, and WM for the cell. The current ratio for the cell is comparatively higher than other cells. The leakage power consumption for the cell is 256 pW, while its read and write power consumption are 6 µW and 1.9 µW, respectively. Also, the cell is half select disturbance-free and therefore supports bit-interleaving. This ensures the increased reliability for the cell. All the aforementioned merits for the cells are achieved with a minimal layout area of 0.553 µm 2 .

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Section: Half Select Disturbance and Soft Error Resiliencementioning

confidence: 99%

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

Rawat

Mittal

2022

Proc. R. Soc. A.

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“…This lower supply voltage brings many problems in SRAM 5 . Several SRAMs have been proposed with the goal for reducing power and enhancing read static noise margin (RSNM) by decoupling the path from storage node 6–10 …”

Section: Introductionmentioning

confidence: 99%

Half‐selection disturbance free 8T low leakage SRAM cell

Lorenzo

Paily

2022

Circuit Theory & Apps

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Summary This work presents a robust and low leakage new 8T static random access memory (SRAM) cell without any half‐selection disturbance. The proposed cell removes write disturbance by eliminating the trail from supply and ground. Furthermore, it removes the read disturbance by separating the read trail from the storage node. The proposed cell addresses the challenge of half select by using different control signals. The cell achieves low leakage because of virtual ground (VGND), series connected tail transistor, and access series stack transistors. To study the usefulness of the proposed SRAM, it is compared with 6T, 10T, 9T, PG9T, 7T, and 8T SRAM cells. The proposed SRAM minimizes leakage power, write power, and read power by 12.4%, 21.62%, and 29.06%. Furthermore, the proposed cell improves read and write noise margin by 57.19% and 19.96%, respectively, as compared to a conventional 6T SRAM. Again, the write energy consumption lowers to about 43.86× while read energy consumption 28.95× as compared to 10T SRAM.

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“…However, reduction in the operation power of SRAM cells remains a challenging issue. This is mainly because the low-power operation of SRAM cell arrays decreases the reliability of memory operation due to disturbances caused by the half selected cell 14 – 16 .…”

Section: Introductionmentioning

confidence: 99%

One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

Choi

Son

Cho

et al. 2021

Sci Rep

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In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

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A low-power single-ended SRAM in FinFET technology

Cited by 69 publications

References 23 publications

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

Half‐selection disturbance free 8T low leakage SRAM cell

One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

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