A low power SoC bus with low-leakage and low-swing technique

Abstract

A novel low power SoC bus with low-leakage and *Off-State Leakage low swing technique is proposed. The repeater used in the bus 2 -Active Power PP . . PP _ Z~~~~~~~~~~~~~V 1.7V 1.5V 1.2V IV 0.9\/ lines effectively reduces leakage power through stacking effect, not losing its logic values even in sleep mode. The proposed ¢ 100 SoC bus reduces not only the leakage power in the normal cL active/sleep mode but also both dynamic and leakage power in the low swing operation mode. The proposed scheme reduces the total power by 44.5% compared to the conventional SoC bus architecture. io 0.25u 0.18u 0.13u 90nm 65nm 45nm