A Low Power Test-per-Clock BIST Scheme through Selectively Activating Multi Two-Bit TRCs

Zhou, Bin; Wu, Xinchun

doi:10.1109/imccc.2014.110

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A Low Power Test-per-Clock BIST Scheme through Selectively Activating Multi Two-Bit TRCs

Cited by 2 publications

References 13 publications

Assessment of Random Testing Circuits Utilizing the LFSR Technique for a Sparse Neural Network

Assessment of Random Testing Circuits Utilizing the LFSR Technique for a Sparse Neural Network

SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST

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