A low supply voltage sensitivity low power oscillator design

Abstract

With the rapid development of social economy, the integrated circuit industry has developed rapidly. At the same time, people’s requirements for the cost, power consumption, integration, stability and other aspects of integrated circuit chips have increased. Oscillators, as an important module for providing clocks to chips, have higher requirements for on-chip oscillators. The purpose of this paper is to achieve a low supply voltage sensitive and low power oscillator. Based on this research purpose, this paper proposes a power adjustment oscillator circuit of the flip level technique, which realizes that the clock signal duty cycle is 50% under the typical case of a supply voltage of 4 V. The center frequency is 512 KHz, of which the process angle trimming range of the capacitor trim circuit is 52.37%-211.28%. With the supply voltage range of 2.5 V to 5.5 V, the clock signal has a frequency variation of 0.299%/V, has low supply voltage sensitivity, and consumes only 400 nA with low power dissipation.