A Low-Voltage-Driven High-Voltage SRAM Pixel Circuit for Power Reduction in a Digital Micro-Display Panel

Cho, Je-Kwang; Jeong, Minsu

doi:10.1109/tcsi.2019.2962820

Cited by 12 publications

(3 citation statements)

References 11 publications

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“…However, in some cases, in a limited size, it is difficult to plug enough capacitance to ensure the output capacity of the pixel unit. Therefore, there are some pure digital pixel driver structures [5,6]. As shown in Fig.…”

Section: Fig2 Dram Pixel Driver Circuit Structurementioning

confidence: 99%

P‐10.5: Design and Comparison of DRAM and SRAM Micro‐LED Pixel Driver Circuits

Zhang

Liu

2023

Symp Digest of Tech Papers

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With the human stepping into the information society and the rapid increase of information, various display facilities and display devices are getting unprecedented development. In the display industry, Micro-LED has become the focus of development because it has the advantages of both traditional LED and small size, and can achieve extremely high PPI. However, it is precisely because of its small size, in order to drive Micro-LED display, it is particularly important to design a separate driver circuit that meets its characteristics. In this paper, different structures of pixel drivers in Micro-LED display driver circuits are studied. By comparing DRAM and SRAM structures, the performance of pixel driver under different frequency conditions is analyzed. This paper introduces and analyzes the circuit structure and design flow of various pixel drivers. Simulation is carried out by Cadence software, and its actual performance is verified by taping out.

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Section: Fig2 Dram Pixel Driver Circuit Structurementioning

confidence: 99%

P‐10.5: Design and Comparison of DRAM and SRAM Micro‐LED Pixel Driver Circuits

Zhang

Liu

2023

Symp Digest of Tech Papers

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“…Moreover, many of these applications demand higher resolution, refresh rate, and color depth [3]. To reduce power and energy consumption, different driving methods have been proposed [4][5][6][7]. In [5], a digital current driving display is proposed that reduces the power consumption by operating the driving transistors in the linear region.…”

Section: Introductionmentioning

confidence: 99%

“…The idea of using a standard CMOS SRAM cell to design a low-power display has been studied for low data rate applications. In [4], new SRAM cells have been proposed that enables a low-voltage row and column driver operation while holding the stored logic at a high-voltage level. The SRAM based displays are power efficient if the application requires a low refresh rate.…”

Section: Introductionmentioning

confidence: 99%