A Markovian Approach for Detecting Failures in the Xilinx SEM core

Rajkumar, Trishna; Öberg, Johnny

doi:10.1109/icfpt56656.2022.9974240

Cited by 3 publications

(1 citation statement)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, since the SEM IP core is directly implemented in the silicon, it is not entirely radiation-proof, as it necessitates elements of the reconfigurable logic to enable the complete utilization of all its features. Currently, there is a paper [21] that presents an error detection scheme for the SEM IP core, which will also be taken into consideration for future firmware development.…”

Section: Jinst 18 P11030mentioning

confidence: 99%

SEU protection design for the prototype readout electronics of MAPS-based STCF inner tracker

Teng,

Feng,

Qin

et al. 2023

J. Inst.

View full text Add to dashboard Cite

The Super Tau Charm Facility (STCF) is a high-luminosity electron-positron collider experiment operating at center-of-mass energy of 2–7 GeV. Its primary goal is to explore flavor physics, CP-violations, and investigate physics beyond the Standard Model. The inner tracker (ITK) is a crucial component of the STCF tracking system, which is responsible for detecting particle hits, especially those with low momentum below 100 MeV/c. Its primary objectives include providing high detection efficiency and spatial resolution for charged particle tracks. However, the electronics of ITK is susceptible to single-event upset (SEU) caused by beam-related background. To address this, this paper presents a prototype of FPGA (Field Programmable Gate Array)-based electronics that can detect and automatically repair SEU induced soft errors in its Configuration Random Access Memory (CRAM) and whose Block Random Access Memory (BRAM) has been also subjected to commonly used hardening techniques. Importantly, the prototype's corrective operations do not result in any dead time due to hot redundancy backup. In the laboratory environment, we measured the bit error rate of the data transmission to be lower than 10-12 with a confidence level of 99.99%. Through neutron beam experiments conducted at China Spallation Neutron Source (CSNS) back-n white neutron source. We demonstrated that the readout electronics can effectively restore correct functionality and promptly rectify soft errors.

show abstract

Section: Jinst 18 P11030mentioning

confidence: 99%

SEU protection design for the prototype readout electronics of MAPS-based STCF inner tracker

Teng,

Feng,

Qin

et al. 2023

J. Inst.

View full text Add to dashboard Cite

show abstract

Investigation of the Xilinx SEM Core on a Zynq-Based Software-Defined Radio Under Proton Irradiation

Stehle,

Budroweit,

Eichstaedt

2023

2023 IEEE Radiation Effects Data Workshop (REDW) (In Conjunction With 2023 NSREC)

View full text Add to dashboard Cite

A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays

Wang,

Li,

Chen

et al. 2024

Sensors

View full text Add to dashboard Cite

Aerospace-grade SRAM-based field-programmable gate arrays (FPGAs) used in space applications are highly susceptible to single event effects, leading to soft errors in FPGAs. Additionally, as FPGAs scale up, the difficulty of correcting soft errors also increases. This paper proposes that performing soft error sensitivity analysis on FPGAs can help target the more sensitive areas for detection and correction, thereby improving the efficiency of soft error repair. Firstly, in accordance with the dual-layer architecture of SRAM-based FPGAs, methods for the soft error sensitivity analysis of FPGA application layer resources and configuration bitstreams are reviewed. Subsequently, based on the analysis results, it also covers corresponding application layer memory scrubbing and configuration scrubbing techniques. A prospective look at emerging soft error mitigation technologies is discussed at the end of this review, supporting the development of highly reliable aerospace-grade SRAM-based FPGAs.

show abstract

A Markovian Approach for Detecting Failures in the Xilinx SEM core

Cited by 3 publications

References 8 publications

SEU protection design for the prototype readout electronics of MAPS-based STCF inner tracker

SEU protection design for the prototype readout electronics of MAPS-based STCF inner tracker

Investigation of the Xilinx SEM Core on a Zynq-Based Software-Defined Radio Under Proton Irradiation

A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays

Contact Info

Product

Resources

About