A Method of Reducing Switch Count in Three-Level Npc Inverter – Analysis in Steady States

Rogowski, Krzysztof; Beniak, Ryszard

doi:10.5277/ped170202

Power Electronics and Drives; Issn 2451-0262 2017

DOI: 10.5277/ped170202

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A Method of Reducing Switch Count in Three-Level Npc Inverter – Analysis in Steady States

Krzysztof Rogowski

Ryszard Beniak

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2020

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Reduced Switch Count in Space Vector PWM for Three-Level NPC Inverter

et al. 2020

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The aim of this paper is to present the real-time implementation and measurements of a reduced switch count in space vector pulse width modulation for three-level neutral point clamped inverters (3L-NPC). We implement space vector pulse width modulation, which uses a prediction algorithm to reduce the number of switches in power transistors (switch count) by up to about 13%. The algorithm applies additional redundant voltage vectors. The method is compute-intensive and was implemented on a dual-core TMS320F28379D digital signal controller. The latest measurements of steady and dynamic states of electric drive, powered by a 3L-NPC inverter using this method, confirmed the possibility of using this method in practical implementation. The implementation and results of the measurements are presented in this paper.

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Reduced Switch Count in Space Vector PWM for Three-Level NPC Inverter

et al. 2020

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A Method of Reducing Switch Count in Three-Level Npc Inverter – Analysis in Steady States

Cited by 1 publication

References 5 publications

Reduced Switch Count in Space Vector PWM for Three-Level NPC Inverter

Reduced Switch Count in Space Vector PWM for Three-Level NPC Inverter

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