A Method of Reducing Switching Losses in Three-Level NPC Inverter

The aim of this paper is to present the real-time implementation and measurements of a reduced switch count in space vector pulse width modulation for three-level neutral point clamped inverters (3L-NPC). We implement space vector pulse width modulation, which uses a prediction algorithm to reduce the number of switches in power transistors (switch count) by up to about 13%. The algorithm applies additional redundant voltage vectors. The method is compute-intensive and was implemented on a dual-core TMS320F28379D digital signal controller. The latest measurements of steady and dynamic states of electric drive, powered by a 3L-NPC inverter using this method, confirmed the possibility of using this method in practical implementation. The implementation and results of the measurements are presented in this paper.

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A Method of Reducing Switching Losses in Three-Level NPC Inverter

Cited by 3 publications

References 7 publications

Simulation and Fault Detection Techniques for Multilevel Inverters used in Smart Grids

Simulation and Fault Detection Techniques for Multilevel Inverters used in Smart Grids

Symmetrical Load of Supply Capacitors with Reduced Switch Count Space Vector PWM for 3L-NPC Inverter

Reduced Switch Count in Space Vector PWM for Three-Level NPC Inverter

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