A methodology for detecting performance faults in microprocessors via performance monitoring hardware

Abstract

Speculative execution of instructions boosts performance in modern microprocessors. Control and data flow dependencies are overcome through speculation mechanisms, such as branch prediction or data value prediction. Because of their inherent self-correcting nature, the presence of defects in speculative execution units does not affect their functionality (and escapes traditional functional testing approaches) but impose severe performance degradation. In this paper, we investigate the effects of performance faults in speculative execution units and propose a generic, software-based test methodology, which utilizes available processor resources: hardware performance monitors and processor exceptions, to detect these faults in a systematic way. We demonstrate the methodology on a publicly available fully pipelined RISC processor that has been enhanced with the most common speculative execution unit, the branch prediction unit. Two popular schemes of predictors built around a Branch Target Buffer have been studied and experimental results show significant improvements on both cases fault coverage of the branch prediction units increased from 80% to 97%. Detailed experiments for the application of a functional self-testing methodology on a complete RISC processor incorporating both a full pipeline structure and a branch prediction unit have not been previously given in the literature.

MT-SBST: Self-test optimization in multithreaded multicore architectures

“…The basic concept of software-based self-testing (SBST) for a single-threaded uniprocessor is described in detail in [12] integer functional units [4], [5], [6], pipeline control logic [7], [8], speculative mechanisms [9] and floating-point units [11]. Today, SBST forms an integral part of the manufacturing test flow [3], [13] of top-end processors, and its role is complementary to other traditional testing methods, either structural like scan-based test or BIST, or functional using external testers [12].…”

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

“…BPU testing has been the subject of a few previous papers, such as [5] and [6]. The former proposes a hardware-based method, which requires the insertion of proper circuitry in the processor for BPU test.…”

“…The latter follows the SBST approach, and mainly focuses on BPUs based on the Branch Target Buffer architecture. In [4] the authors report a very convincing analysis of faults affecting BPUs, and propose the usage of performance counters to detect them. However, the proposed method does not achieve full coverage of stuck-at faults, and requires very long test times.…”

A SBST strategy to test microprocessors' Branch Target Buffer

“…This particular issue makes Branch prediction Units (BPUs) hard to test by functional means. In [4] a SBST methodology to deal with this kind of faults in BTB-based prediction units accessed via a hash function was proposed: the method resorts to performance monitoring hardware in order to observe the test program responses; the fault coverage reaches 97%, taking about 20,000 clock cycles. A pure functional test for Branch History Table (BHT)-based branch prediction units is presented in [5]: the approach exploits processor instructions to implement an algorithm largely used in memory testing to fully test the decoding logic of a memory; the algorithm obtains a 100% fault coverage and is suitable for different implementations of the considered unit.…”