A Methodology for Implementation of the Execution Phase of Artificial Neural Networks in Digital Hardware Devices

Abstract

In this paper we describe a methodology for implementing the phase of execution of Artificial Neural Networks (ANN) in hardware devices. First, we show how the elements of a single neuron: multipliers, sum of products and transfer function are separated and constructed as VHDL entities. These entities are then interconnected to form a neuron that can be mapped to a hardware device. Using a similar approach, neurons are grouped in layers, which are then interconnected themselves to construct an Artificial Neural Network. The methodology is intended to lead a Neural Network designer through the steps required to take the design into a hardware device, starting with the results provided by a neurosimulator, obtaining the network parameters and translating them into a fully synthesizable design. A prototype of a Java-based ANN descriptor to VHDL translator is presented. In addition, the desired characteristics of neurosimulators are discussed and a comparison among different hardware platforms is shown.