A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

Kelefouras, Vasilios; Athanasiou, George S.; Alachiotis, N.; Michail, Harris E.; Kritikakou, Angeliki; Goutis, C.E.

doi:10.1109/tsp.2011.2168525

Cited by 10 publications

(13 citation statements)

References 16 publications

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“…A comparison with the above libraries would be unfair because they use the SIMD (Single Instruction Multiple Data) vector instructions (they support load/store and arithmetical instructions with 128/256-bit data); however, our future work includes the support of SIMD instructions. In [29] [30] [31] [32], we have developed algorithm specific methodologies (we used the SIMD instructions), which produce lower execution time, lower compilation time and lower number of data accesses, than ATLAS [29] [30], FFTW [30] and OpenCV [32]. A comparison between the proposed methodology and [29] [30], is made in Section 4.…”

Section: Related Workmentioning

confidence: 99%

A methodology for speeding up loop kernels by exploiting the software information and the memory architecture

Kelefouras

Kritikakou

Goutis

2015

Computer Languages, Systems & Structures

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International audienceIt is well-known that today׳s compilers and state of the art libraries have three major drawbacks. First, the compiler sub-problems are optimized separately; this is not efficient because the separate sub-problems optimization gives a different schedule for each sub-problem and these schedules cannot coexist as the refining of one, causes the degradation of another. Second, they take into account only part of the specific algorithm׳s information. Third, they take into account only a few hardware architecture parameters. These approaches cannot give an optimal solution.In this paper, a new methodology/pre-compiler is introduced, which speeds up loop kernels, by overcoming the above problems. This methodology solves four of the major scheduling sub-problems, together as one problem and not separately; these are the sub-problems of finding the schedules with the minimum numbers of (i) L1 data cache accesses, (ii) L2 data cache accesses, (iii) main memory data accesses, (iv) addressing instructions. First, the exploration space (possible solutions) is found according to the algorithm׳s information, e.g. array subscripts. Then, the exploration space is decreased by orders of magnitude, by applying constraint propagation to the software and hardware parameters.We take the C-code and the memory architecture parameters as input and we automatically produce a new faster C-code; this code cannot be obtained by applying the existing compiler transformations to the original code. The proposed methodology has been evaluated for five well-known algorithms in both general and embedded processors; it is compared with gcc and clang compilers and also with iterative compilation

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Section: Related Workmentioning

confidence: 99%

A methodology for speeding up loop kernels by exploiting the software information and the memory architecture

Kelefouras

Kritikakou

Goutis

2015

Computer Languages, Systems & Structures

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“…Common VLSI implementation of FFT architectures can be classified into three categories: memory-based architectures [3,4,5,6], cache-based architectures [7,8,9] and pipelined architectures [10,11,12,13]. Memory-based architectures generally consist of processing units and memory blocks.…”

Section: Introductionmentioning

confidence: 99%

An ultra-long FFT architecture implemented in a reconfigurable application specified processor

Feng

Wang

et al. 2016

IEICE Electron. Express

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This paper presents an efficient architecture for performing 128 points to 1M points Fast Fourier Transformation (FFT) based on mixed radix-2/4/8 butterfly unit. The proposed FFT architecture reduces the computation cost by taking the advantage of the radix-8 FFT algorithm while remaining compatible with sequences whose data length is an integral power of 2. Further optimizations for reconfigurable application specified processor are developed. First, we propose a separated radix-2/4/8 butterfly unit which is more flexible than an entire radix-2/4/8 butterfly unit; second, for the sequences longer than 256K points, an efficient 2-epoch FFT solution is realized. This FFT architecture is implemented in a reconfigurable application specified processor. The computation time of our architecture is 676 us and 14.8 ms for 128K and 1M points FFTs respectively.

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“…On the other hand, the FFT performance is tightly dependent to the processor's architecture and its memory and cache structure. Kelefouras et al [24] propose a methodology to speed up the FFT algorithm depending on the memory hierarchy of processor's architecture. State-of-the-art FFT libraries such as FFTW [25][26][27] and UHFFT [28] maximize the performance by adapting to the hardware at run time, usually using a planner, searching over a large space of parameters in order to pick the best implementation.…”

Section: Introductionmentioning

confidence: 99%

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

Bahtat

Belkouch

Elleaume

et al. 2016

EURASIP J. Adv. Signal Process.

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The fast Fourier transform (FFT) is perhaps today's most ubiquitous algorithm used with digital data; hence, it is still being studied extensively. Besides the benefit of reducing the arithmetic count in the FFT algorithm, memory references and scheme's projection on processor's architecture are critical for a fast and efficient implementation. One of the main bottlenecks is in the long latency memory accesses to butterflies' legs and in the redundant references to twiddle factors. In this paper, we describe a new FFT implementation on high-end very long instruction word (VLIW) digital signal processors (DSP), which presents improved performance in terms of clock cycles due to the resulting low-level resource balance and to the reduced memory accesses of twiddle factors. The method introduces a tradeoff parameter between accuracy and speed. Additionally, we suggest a cache-efficient implementation methodology for the FFT, dependently on the provided VLIW hardware resources and cache structure. Experimental results on a TI VLIW DSP show that our method reduces the number of clock cycles by an average of 51 % (2 times acceleration) when compared to the most assembly-optimized and vendor-tuned FFT libraries. The FFT was generated using an instruction-level scheduling heuristic. It is a modulo-based register-sensitive scheduling algorithm, which is able to compute an aggressively efficient sequence of VLIW instructions for the FFT, maximizing the parallelism rate and minimizing clock cycles and register usage.

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A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

Cited by 10 publications

References 16 publications

A methodology for speeding up loop kernels by exploiting the software information and the memory architecture

A methodology for speeding up loop kernels by exploiting the software information and the memory architecture

An ultra-long FFT architecture implemented in a reconfigurable application specified processor

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

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