A Methodology for the Synthesis and Evaluation of Hardware Accelerators

Abstract

The methodology presented in this paper is based on a system of software automation tools that enable rapid design, implementation and evaluation of hardware accelerators. This system leverages a set of available industry-grade frameworks that can generate hardware implementations of software-described algorithms and computations. The hardware accelerators undergo an evaluation process that highlights the capabilities of the frameworks used to generate them. The methodology and its components could act as a building block for a larger system that performs design space exploration (DSE). The input to the system are mathematical computations described in two different formats: in Operator Language, and, as a Simulink Model, respectively. The system then is capable of generating a set of programs describing the solution implementation in either a lower-level language (e.g. C/C++) or a hardware description language.