A methodology of implementing medium access protocols using a general parameterized architecture

Iliopoulos, Marios; Antonakopoulos, Theodore

doi:10.1109/iwrsp.2000.854974

Cited by 5 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The dynamic ARM processor contains the same set of instructions with the static version but part of the instruction set is executed dynamically using the scheduler described in the previous section. Two MAC processing systems were tested using the emulation platform, the IEEE802.11 [9] and the IEEE802.3 MAC protocol [10] with the addition of the scheduler and a monitor module, which traced exchanged signals and recorded statistical information. The monitor module recognized instructions and different scheduler modes (cache-miss, cache-hit, staticinstruction) and gathered statistical information for the size and the content of the instruction cache, the forecast instruction performance, like the number of cachemisses, the number of cycles that the processor is in HOLD state, etc.…”

Section: Resultsmentioning

confidence: 99%

Run-Time Optimized Reconfiguration Using Instruction Forecasting

Iliopoulos

Antonakopoulos

2001

Field-Programmable Logic and Applications

View full text Add to dashboard Cite

Abstract. The extensive use of reconfigurable computing devices has imposed a new category of processors, the dynamic instruction set processors (DISPs) that customize their instruction sets dynamically to the application needs. One of the major drawbacks of DISPs is the reconfiguration time needed to alter the instruction set, which is directly added to the program execution time discouraging the use of DISPs especially for time critical processing applications. This paper introduces a methodology for optimizing reconfiguration time through instruction forecasting and presents the results obtained when applying this method to Medium Access processing systems that execute time critical network tasks.

show abstract

Section: Resultsmentioning

confidence: 99%

Run-Time Optimized Reconfiguration Using Instruction Forecasting

Iliopoulos

Antonakopoulos

2001

Field-Programmable Logic and Applications

View full text Add to dashboard Cite

show abstract

“…Another paper by the same author describes a methodology to implement medium access protocol based on a microprocessor core and a general parameterized architecture containing configurable hardware blocks [36]. The con-…”

Section: Comments On the Wireless Analysismentioning

confidence: 99%

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Nabi

Wells

Vanderbauwhede

2008

2008 IEEE International SOC Conference

View full text Add to dashboard Cite

Nabi, Syed Waqar (2009) A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices. EngD thesis.http://theses.gla.ac.uk/865/ Copyright and moral rights for this thesis are retained by the author A copy can be downloaded for personal non-commercial research or study, without prior permission or charge This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the Author The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the Author When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given Copyright c Syed Waqar Nabi October 2008In the name of Allah, the Beneficent, the Merciful.Read: In the name of thy Lord Who createth, Createth man from a clot. Read: And thy Lord is the Most Bounteous, Who teacheth by the pen, Teacheth man that which he knew not. Nay, but verily man is rebellious That he thinketh himself independent! Lo! unto thy Lord is the return.The Quran; Chapter 96, Verses 1-7 i Abstract DRMP, a Dynamically Reconfigurable MAC Processor, is an innovative, dynamically reconfigurable System-on-Chip architecture. The architecture exploits substantial overlaps in the functionality of different wireless MAC layers. Its flexibility is specialized for addressing the requirements of the MAC layer of wireless standards. It is targeted at consumer, multi-standard, handheld devices, and its design is meant to address the balance of flexibility and power-efficiency that this target market demands. The DRMP reconfigures packet-by-packet on the fly, allowing execution of concurrent protocol modes on a single hardware co-processor. An interrupt-driven programming model has also been presented and shown to implement the protocol state-machine of the three protocols on a CPU. These features will allow the DRMP to replace three MAC processors in a hand-held device. The most innovative component of the DRMP architecture is its Interface and Reconfiguration Controller. It uses a combination of asynchronous controllers to dynamically reconfigure the functional units in the architecture and delegate MAC tasks to them. The architecture has been modeled in Simulink at cycle-approximate abstraction. Results of simulations involving transmission and reception of packets have been presented, showing that the platform concurrently handles three protocol streams, reconfigures dynamically, yet meets and exceeds the protocol timing constraints, all at a moderate frequency. Its heterogeneous and coarse-grained functional units, limited connectivity requirements between these units, and proportionally large time that these resources are idle, promise a very modest power-consumption, suitable for mobile devices, while offering flexibility to implement different MAC protocols. The Institute of System Level Integration in general, the EngD center and Sian Williams in particular, deserve a special t...

show abstract

Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits

Iliopoulos

Antonakopoulos

2000

Lecture Notes in Computer Science

View full text Add to dashboard Cite

A methodology of implementing medium access protocols using a general parameterized architecture

Cited by 5 publications

References 0 publications

Run-Time Optimized Reconfiguration Using Instruction Forecasting

Run-Time Optimized Reconfiguration Using Instruction Forecasting

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits

Contact Info

Product

Resources

About