A Methodology to Evaluate the Energy Efficiency of Application Specific Processors

Beucher, Nicolas; Belanger, N.; Savaria, Yvon; Bois, Guy

doi:10.1109/icecs.2007.4511157

Cited by 3 publications

(5 citation statements)

References 6 publications

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“…Interestingly, for both core and total energy, the factor of improvement is close to and higher than the relative AT product in all cases. This may support the idea that the relative AT product is a reliable and pessimistic estimator for the improvement in energy consumption, as was previously suggested [32], [33]. In our sample of seven algorithms, there is a high correlation between the energy improvement factor and the relative AT product.…”

Section: Energysupporting

confidence: 87%

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Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

Aubertin

Langlois

Savaria

2012

IEEE Trans. VLSI Syst.

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This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inherent to the target algorithm class. An appropriate choice of custom instructions and application-specific registers is used together with a very long instruction word architecture in order to mimic a pipelined systolic array. This leads to a processing speed close to the limit imposed by memory bandwidth constraints. For three intra-field deinterlacing algorithms and 2-D convolution with four kernel sizes, the design approach yields speedup factors between 36 and 1330, Area-Time (AT) product improvements between 12 and 243 , and energy consumption reduction factors between 13 and 262.

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Section: Energysupporting

confidence: 87%

“…is the subset of image , where (31) such that (32) which implies (33) that is, is either if or extended to the right by blocks of pixels if .…”

Section: F Implementation Parametersmentioning

confidence: 98%

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

Aubertin

Langlois

Savaria

2012

IEEE Trans. VLSI Syst.

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“…Simulations are performed to monitor the switching activity and to extract the power consumption values for each processor, with and without the defined instructions (P o ). The energy consumption is then deduced and comparisons were made, based on [8]. The conclusions of this work will be also valid for ASIC, as the energy ratios, as opposed to the absolute values, are studied.…”

Section: A Platform Technologymentioning

confidence: 98%

“…Dividing the equation by the core power P, results into: (8) In which P o is the normalized power-overhead of system, i.e. the ratio of P e /P.…”

Section: B Platforms Without Power Gatingmentioning

confidence: 99%

Estimation of energy performance in computing platforms

Zarrabi

Al-Khalili

Savaria

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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System-level estimation of speed and energy performance is a key step in design space exploration of lowenergy and high-performance VLSI systems. While low-level simulation-based analysis can be too time-consuming to obtain performance elements, system-level models that can quickly and accurately estimate these elements are very valuable. In this work, models for energy performance estimation of computing platforms are proposed. The proposed energy performance models are inspired by Amdahl's law. The models consider platform models based on the support of power gating. Analytical results show that the upper-bound of energy performance, according to the application profile is the "resolute" (that cannot be enhanced) segment of the (embedded) software application. This is a similar concern to the one seen for "net acceleration" (the speed performance) being bounded by the "sequential" segment, according to Amdahl's law. Experimental results demonstrate that large improvements in energy performance may be obtained using power gating for both data and control dominated classes of applications (2 and 12 folds respectively). The results also demonstrate an average error of 22% between the proposed system-level models and true experimental results for three classes of applications.

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“…Additionally, more and more IoT systems are working in battery-powered scenarios or even battery-less scenarios [ 2 , 3 ]. Given the limitation of energy supply and the demand for performance, system designers are paying more attention to power consumption, especially for the embedded processor which is one of the core components in IoT systems [ 4 , 5 ]. Due to its responsibility for data computation and system control, an embedded processor has to deal with a variety of complicated tasks with different workloads, making it difficult to balance peak performance and power consumption for various scenarios.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

Qiao

Gao

et al. 2021

Micromachines

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Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 W, 59.7 W and 71.1 W. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.

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A Methodology to Evaluate the Energy Efficiency of Application Specific Processors

Cited by 3 publications

References 6 publications

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

Estimation of energy performance in computing platforms

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

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