A Minimally Invasive 64-Channel Wireless μECoG Implant

Abstract

Emerging applications in brain-machine interface systems require high-resolution, chronic multisite cortical recordings, which cannot be obtained with existing technologies due to high power consumption, high invasiveness, or inability to transmit data wirelessly. In this paper, we describe a microsystem based on electrocorticography (ECoG) that overcomes these difficulties, enabling chronic recording and wireless transmission of neural signals from the surface of the cerebral cortex. The device is comprised of a highly flexible, high-density, polymer-based 64-channel electrode array and a flexible antenna, bonded to 2.4 mm × 2.4 mm CMOS integrated circuit (IC) that performs 64-channel acquisition, wireless power and data transmission. The IC digitizes the signal from each electrode at 1 kS/s with 1.2 μV input referred noise, and transmits the serialized data using a 1 Mb/s backscattering modulator. A dual-mode power-receiving rectifier reduces data-dependent supply ripple, enabling the integration of small decoupling capacitors on chip and eliminating the need for external components. Design techniques in the wireless and baseband circuits result in over 16× reduction in die area with a simultaneous 3× improvement in power efficiency over the state of the art. The IC consumes 225 μW and can be powered by an external reader transmitting 12 mW at 300 MHz, which is over 3× lower than IEEE and FCC regulations.

Silicon-Integrated High-Density Electrocortical Interfaces

“…For example, several dc-coupling IAs have been demonstrated in order to avoid external accoupling capacitors at the input of the AFE [42], [43]. In these designs, electrode offsets are canceled by feedback currents via a dc-servo loop [42], [43] or by capacitive feedback [66].…”

“…Thus far, chips with approximately 100-300 data acquisition channels have been reported [54], [67]- [70]. One of the strategies to reduce area and power consumption in order to maximize channel density is the use of scaled processes such as 65-nm complementary metal-oxidesemiconductor (CMOS) [66], achieving 64 channels with a silicon area of 0.025 mm 2 per channel. For higher density, in some designs, a SAR ADC is shared by about 8-16 AFEs using a time multiplexer [54].…”

“…In doing so, power-efficient multiplexers [71] and time-interleaving sample-and-hold circuits in SAR ADCs have been demonstrated. Alternatively, a dedicated ADC per AFE channel has been also pursued due to its ease of integration with a larger number of channels [44], [66].…”

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

“…Ideally, in a differential measurement, two identical electrodes should cancel-out their half-cell potentials [15]. In practice, a random differential electrode offset, up to hundred millivolts, can appear [4], [13], [16], [17]. Moreover, the situation is worsened when the recording functionality is combined with the brain stimulation, where a build-up of charge occurs between electrodes [18]- [20], as well as undesired in-band stimulation artifacts [16], [17].…”

“…The main disadvantage of these approaches is that the cut-off frequency of each recording channel is prone to different variations [4]. A digitally assisted servo loop can be used to overcome this issue by controlling the corner frequency in the digital domain [4], [13], [27]- [29]. However, the stability of a digitally assisted servo loop is impacted by the latency of the digital filter.…”