A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC

Erdmann, Christophe; Verbruggen, Bob; Vaz, B.; Pelliconi, Roberto; McGrath, John; Kinnerk, Ryan; Torre, Ronnie De La; O'Dwyer, John M.; Lynch, Pat; Kelly, P.F.; Lim, Peng; Breathnach, Daire; Farley, Brendan

doi:10.1109/vlsic.2018.8502292

Cited by 9 publications

(2 citation statements)

References 4 publications

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“…In wireless communication, scientists are working to deliver low latency audio, video and data for LTE/5G applications (Rappaport et al , 2013). Additionally, latency can be measured using the timing reference signal (Erdmann et al , 2018). The fast-sampling clock generation from the PLL can help initiate the reference signal.…”

Section: Theoretical Analysismentioning

confidence: 99%

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

Faheem

Azeem

Minhas

et al. 2022

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Purpose RF transceiver module is considered a vital part of any wireless communication system. This module consists of two important parts the RF transceiver and analog-to-digital converter (ADC). Usually, both these parts – RF transceiver and ADC – are used to enhance the perspective of size and power. The data processing in 4G communication makes hurdles and need research attention to make it faster and smaller in size. Accuracy and fast processing are the critical challenges in the modern communication system. Design/methodology/approach After theoretical and practical investigations, this research work proposes key new techniques for the RF transceiver module. These techniques will make RF transceiver small, power-efficient and on the other hand, make dual SAR-ADC more effective as well. The proposed design has no intermediate frequency where the RF transceiver is reduced its major blocks from five to four, which includes crystal oscillator, phase lock loop, power amplifier and low noise amplifier. Moreover, the shared circuitry is introduced in the architecture of the SAR-ADC for the production of dual outputs, specifically in bootstrapped switch and comparator. Findings The miniaturized RF transceiver and SAR-ADC are well tested separately before the plantation on the printed circuit board (PCB). The operating voltage and frequency of the RF transceiver module are 1.2 V and 5.8 GHz, where the sampling rate, bandwidth and output power are 25 MHz, 200 MHz and 5 dBm, respectively. The core area of the PCB is 58.13 mm2. The bandwidth efficiency is 93% using surface acoustic wave less transmitter. The circuit is based on the library of 90 nm CMOS technology. Originality/value The entire circuit is highly synchronized with the input and reference clocks to avoid self-interference.

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Section: Theoretical Analysismentioning

confidence: 99%

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

Faheem

Azeem

Minhas

et al. 2022

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“…Parallel sampling technology has witnessed rapid development over the past few decades, as indicated by various studies [1][2][3].This technique leverages interleaved sampling in either the time or frequency domain to increase the sampling rate and bandwidth. Consequently, it caters to the requirements of fields such as communication, nuclear physics experiments, and electronic measurements, which demand high-speed sampling systems [4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

An efficient calibration method for digital bandwidth interleaving sampling system

Ma,

Wu,

Jiang

et al. 2023

J. Inst.

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Digital bandwidth interleaving (DBI) is a technique that can simultaneously increase system sampling rate and bandwidth. While DBI can reduce the impact of clock jitter on the dynamic performance of the system compared to time-interleaved sampling systems, achieving dynamic performance comparable to time-interleaved analog-to-digital converters (TIADC) remains challenging due to phase misalignment in crossover bands caused by analog filters and nonlinearity in analog mixers. To address these issues, this paper proposes a method to calibrate DBI sampling systems using PRBS signals. This method involves injecting pseudo-random binary sequence (PRBS) signal into the system input as a background signal and calculating the correlation between the output sampling sequence and the PRBS sequence to obtain the response of each sampling channel. Compared with traditional single tone signal or pulse signal, this method offers a more efficient background calibration method. To verify the effectiveness of this method, this paper designed a hybrid parallel sampling system combining DBI and TIADC with a 20 GSPS sampling rate and 8 GHz bandwidth to evaluate the effectiveness of the calibration method. In the performance test of the sampling system before and after calibration, this calibration method improved the system's Signal-to-Noise and Distortion Ratio (SINAD) by up to 13 dB, Spurious Free Dynamic Range (SFDR) by up to 27 dB, and phase response flatness better than 0.3 radians.

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High-Speed ADCs for Wireless Base Stations

Verbruggen

Vaz

Erdmann

et al. 2019

Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits

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A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC

Cited by 9 publications

References 4 publications

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

Key techniques of ultra-low-power ADC and miniaturized RF transceiver circuits for 4G/LTE applications

An efficient calibration method for digital bandwidth interleaving sampling system

High-Speed ADCs for Wireless Base Stations

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