A Multi-Phase Time-to-Digital Converter Differential Vernier Ring Oscillator

Annagrebah, Amina; Bechetoille, E.; Laktineh, I. B.; Chanal, H.

doi:10.1109/uemcon47517.2019.8992933

Cited by 2 publications

(1 citation statement)

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“…Basically, the delay line in the Vernier TDC can be roughly divided into three categories. The first kind of delay line is composed of typical inverters without feedback adjustment circuits [ 4 , 5 , 6 , 7 , 8 ]. This kind of delay line has a simple structure, but cannot deal with PVT variations, so its robustness needs to be improved.…”

Section: Introductionmentioning

confidence: 99%

A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

Tong

Wang

Zhang

et al. 2021

Sensors

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This paper presents a low jitter All-Digital Delay-Locked Loop (ADDLL) with fast lock time and process immunity. A coarse locking algorithm is proposed to prevent harmonic locking with just a small increase in hardware resources. In order to effectively solve the dithering phenomenon after locking, a replica delay line and a modified binary search algorithm with two modes were introduced in our ADDLL, which can significantly reduce the peak-to-peak jitter of the replica delay line. In addition, digital codes for a replica delay line can be conveniently applied to the delay line of multi-channel Vernier TDC while maintaining consistency between channels. The proposed ADDLL has been designed in 55 nm CMOS technology. In addition, the post-layout simulation results show that when operated at 1.2 V, the proposed ADDLL locks within 37 cycles and has a closed-loop characteristic, the peak-to-peak and root-mean-square jitter at 800 MHz are 6.5 ps and 1.18 ps, respectively. The active area is 0.024 mm2 and the power consumption at 800 MHz is 6.92 mW. In order to verify the performance of the proposed ADDLL, an architecture of dual ADDLL is applied to Vernier TDC to stabilize the Vernier delay lines against the process, voltage, and temperature (PVT) variations. With a 600 MHz operating frequency, the TDC achieves a 10.7 ps resolution, and the proposed ADDLL can keep the resolution stable even if PVT varies.

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