A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS

Choke, Tieng Ying; Zhang, Huajiang; Tan, Sam Chun Geik; Yang, Wei; Tan, Ying Chow; Karri, Ramesh; Sun, Dong; Li, Qing; Lee, Zwei-Mei; Gao, Peng; Shu,; Shanaa, Osama

doi:10.1109/jssc.2013.2254531

Cited by 19 publications

(7 citation statements)

References 9 publications

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“…For the oscillator in [26], implemented in a 0. 35 CMOS technology and biased from 2.5 V, the peak FoM of 195.4 dBc/Hz is reached with a of 81% for a peak swing of 6.4 V (computed from the values of tank , inductor and current provided in the paper). Large voltages can seriously damage the transistors and reduce significantly their lifetime [32], [33].…”

Section: Excess Noise Factor In Lc-tank Oscillatorsmentioning

confidence: 99%

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering

Garampazzi¹,

Mendes

Codega³

et al. 2015

IEEE J. Solid-State Circuits

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A complementary p-n class-B oscillator with two magnetically coupled second harmonic tail resonators is presented and compared to an N-only reference one. An in depth analysis of phase noise, based on direct derivation of the Impulse Sensitivity Function (ISF), provides design insights on the optimization of the tail resonators. In principle the complementary p-n oscillator has the same optimum Figure of Merit (FoM) of the N-only at half the voltage swing. At a supply voltage of 1.5 V, the maximum allowed oscillation amplitude of the N-only is constrained, by reliability considerations, to be smaller than the value that corresponds to the optimum FoM even when 1.8 V thick oxide transistors are used. For an oscillation amplitude that ensures reliable operation and the same tank, the p-n oscillator achieves a FoM 2 to 3 dB better than the N, only depending on the safety margin taken in the design. After frequency division by 2, the p-n oscillator has a measured phase noise that ranges from 150.8 to 151.5 dBc/Hz at 10 MHz offset from the carrier when the frequency of oscillation is varied from 7.35 to 8.4 GHz. With a power consumption of 6.3 mW, a peak FoM of 195.6 dBc/Hz is achieved.

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Section: Excess Noise Factor In Lc-tank Oscillatorsmentioning

confidence: 99%

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering

Garampazzi¹,

Mendes

Codega³

et al. 2015

IEEE J. Solid-State Circuits

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“…Traditional harmonic rejection receiver only has three hard-wired mixer paths [1,4], which cannot tolerate phase ambiguity. In this paper, a harmonic rejection mixer which tolerate phase ambiguity is proposed.…”

Section: B Phase Ambiguity Correctionmentioning

confidence: 99%

“…One of the major challenges of SDR receivers is how to receive the desired signals when strong harmonic interference exists, which is more severe for TV receivers [1]. The harmonic rejection mixer has been proven to be effective to solve this problem.…”

Section: Introductionmentioning

confidence: 99%

A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration

Zhang

Wang

Chi

2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 0.1-1.5GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity, and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8 phase local oscillating (LO) generator, the highest carrier frequency from the frequency synthesizer is only twice of the desired LO frequency. The HR receiver has been implemented in 65nm CMOS. With 1.8mm 2 core chip area and 5.4-24.5mA current consumption from a 1.2V power supply, the receiver achieves 85dB conversion gain, 4.3dB NF, +13dBm/+14dBm IB/OB-IIP3, >54/56 dB HR3/HR5 with 30-40dB improvement by calibration, and 2.3% EVM with 32QAM modulation signal.

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“…Using the off-chip channel tracking filter to filter the block signal is an easy way, but the whole system is not compact and the chip needs more interface circuits [1]. TV tuner based on high dynamic range RF variable gain amplifier (VGA) has been developed in [2].…”

Section: Introductionmentioning

confidence: 99%

A 95 dB dynamic range automatic gain control circuits and systems for Multi-standard Digital TV tuner

Zheng

Ma³

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 95 dB dynamic range automatic gain control (AGC) circuits and systems for Multi-standard Digital TV (DTV) tuner has been presented. A novel automatic gain control method composed of RFAGC and IFAGC is proposed with improved SNR. A wideband single-ended LNA based on current-reuse technique with low temperature variation is proposed. The complete AGC circuits are fabricated in six-metal 0.18-µm CMOS technology and consume DC current of 32.5 mA from a 1.8 V supply. The RF front-end circuit achieves 90 dB maximum gain, 95 dB gain control range, a 4 dB noise figure and an IIP3 higher than -28 dBm at the maximum gain.

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A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS

Cited by 19 publications

References 9 publications

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering

A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration

A 95 dB dynamic range automatic gain control circuits and systems for Multi-standard Digital TV tuner

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A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS

Cited by 19 publications

References 9 publications

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering

A 0.1&#x2013;1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration

A 95 dB dynamic range automatic gain control circuits and systems for Multi-standard Digital TV tuner

Contact Info

Product

Resources

About

A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration