A Nanosecond–Level Hybrid Table Design for Financial Market Data Generators

Abstract

This paper proposes a hybrid sorted table design for minimizing electronic trading latency, with three main contributions. First, a hierarchical sorted table with two levels, a fast cache table in reconfigurable hardware storing megabytes of data items and a master table in software storing gigabytes of data items. Second, a full set of operations, including insertion, deletion, selection and sorting, for the hybrid table with latency in a few cycles. Third, an ondemand synchronization scheme between the cache table and the master table. An implementation has been developed that targets an FPGA-based network card in the environment of the China Financial Futures Exchange (CFFEX) which sustains 1-10Gb/s bandwidth with latency of 400 to 700 nanoseconds, providing an 80-to 125-fold latency reduction compared to a fully optimized CPU-based solution, and a 2.2-fold reduction over an existing FPGA-based solution.

A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency

“…A CPU-FPGA hybrid sorted table to support the storage of order book in the range of gigabytes with a latency of nanosecond level is shown in the work of Fu et al (2017). The FPGA cache table stores the top of the order book, while the other positions are stored in the host memory.…”