A Negative Feedback Looped Voltage-Controlled Ring Oscillator With Frequency Voltage Converter

Choi, Young-Shig

doi:10.1109/tmtt.2013.2276055

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Architecture Of Dll With Two Negative Feedback Loops1

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Cited by 6 publications

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“…The operation of two negative feedback loops in a DLL results in suppressing the jitter of clock signal generated by the proposed DLL. The circuit of DVVC, a modified FVC in [7], is shown in Fig. 4.…”

Section: Architecture Of Dll With Two Negative Feedback Loopsmentioning

confidence: 99%

A Low-Jitter DLL-Based Clock Generator with Two Negative Feedback Loops

Choi¹,

Park²

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal 0.18 µm CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

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Section: Architecture Of Dll With Two Negative Feedback Loopsmentioning

confidence: 99%