A new approach to statistical process control in a test environment: the empirical delta control chart

Abstract

In the past several years, the use of statistical process control (SPC) has mushroomed within the semiconductor industry, particularly in the wafer fabrication environment. The complexity and length of a semiconductor fabrication process demands the stability assessment and unit process control which SPC provides so well. More recently, the use of SPC has also begun in the semiconductor test areas -wafer multiprobe and package test. The multiprobe stage of the test process determines which die on the wafer are functioning to avoid the cost of assembling and testing nonfunctional die. Package test involves a parametric assessment of the goodness of the device versus customer specifications. Historically speaking, the test environment has been very difficult to control. From a statistical point of view, however, test is little more than a measurement process and SPC can be used to verify that a particular test set-up (including both test hardware and test system) is functioning, or measuring, as expected. A major barrier in the past, however, was that lot-to-lot differences resulting from variability in the wafer fabrication process tended to mask measurement reproducability problems. One solution to this comes in the form of control wafers or control devices which theoretically do not change and are tested prior to every run. A much better solution is to enhance this control strategy with SPC, whereby control charts can be utilized to monitor and interpret the control device/wafer results. In this article, we will cover past attempts at Harris Semiconductor to control the test measurement process along with their inherent weaknesses. With this, the Empirical Delta Control Chart, along with its corresponding control unit/die philosophy, is introduced as a superior alternative toward controlling the semiconductor wafer and package test environments. Life Without ControlsInitially, checks of test equipment were limited to periodic calibrations. In the majority of instances, adjustments and corrections to the test systems and hardware did not take place until a problem occurred while testing. The effect of this was shutting down the line and launching maintenance personnel into a frenzied search for the cause of the problem so testing could resume. This haphazard approach was fostered by the idea that test set-ups were inherently identical with respect to the evaluation of the product. Any differences in test results were ignored or attributed to variation in the process lots, or batches, coming from the wafer fabrication area. This leads to circumstances where product found to be good at one stage of the testing process is later found to be defective -often by the customer. The invisible side of this "out of control" situation is the lost revenue of product falsely rejected. A somewhat improved, yet still severely limited, attempt to solve test problems is the institution of minimum test yields on lots.If testing a particular lot of wafers or packaged parts results in a lower than expected yield, then the lot is held...