A new FPGA based architecture to improve performance of deflectometry image processing algorithm

Bhatti, Faraz; Greiner, Thomas; Heizmann, Michael; Ziebarth, Mathias

doi:10.1109/tsp.2017.8076049

Cited by 5 publications

(1 citation statement)

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“…In literature, various researchers have employed FPGA for image processing applications [20][21][22][23][24]. The authors of [25] presented an FPGA hardware architecture for real-time disparity map computation.…”

Section: Related Workmentioning

confidence: 99%

Design of an FPGA Hardware Optimizing the Performance and Power Consumption of a Plenoptic Camera Depth Estimation Algorithm

Bhatti¹,

Greiner²

2021

Algorithms

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Plenoptic camera based system captures the light-field that can be exploited to estimate the 3D depth of the scene. This process generally consists of a significant number of recurrent operations, and thus requires high computation power. General purpose processor based system, due to its sequential architecture, consequently results in the problem of large execution time. A desktop graphics processing unit (GPU) can be employed to resolve this problem. However, it is an expensive solution with respect to power consumption and therefore cannot be used in mobile applications with low energy requirements. In this paper, we propose a modified plenoptic depth estimation algorithm that works on a single frame recorded by the camera and respective FPGA based hardware design. For this purpose, the algorithm is modified for parallelization and pipelining. In combination with efficient memory access, the results show good performance and lower power consumption compared to other systems.

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