A new low-power dynamic circuit for wide fan-in gates

Asyaei, Mohammad

doi:10.1016/j.vlsi.2017.10.010

Cited by 24 publications

(8 citation statements)

References 21 publications

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“…Table 2 shows the power-delay product, unity noise gain (UNG) comparisons of two-input EX-OR gate and 4:1 MUX with low power dynamic keeper 15 and PCK logic. From the table, we can examine that the proposed PCK has a reduced power-delay product of 21% for two-input EX-OR gate and 14% power-delay product for 4:1 MUX as compared with the low power dynamic logic circuit (Figure 11).…”

Section: Resultsmentioning

confidence: 99%

“…From the table, we can examine that the proposed PCK has a reduced power-delay product of 21% for two-input EX-OR gate and 14% power-delay product for 4:1 MUX as compared with the low power dynamic logic circuit (Figure 11). 15…”

Section: Resultsmentioning

confidence: 99%

“…Figure 7 shows the two-input OR gate with domino logic with complement CLK keeper 15 circuit. When clk = “0,” the dynamic node is pre-charged to V DD through the MP2 transistor.…”

Section: Limitations Of Existing Keeper–based Domino Circuitsmentioning

confidence: 99%

“…Due to the stacking effect of the diode footed domino (DFD) keeper 14 circuit, the evaluation delay is increased. The proposed logic in Asyaei 15 is less noise tolerant due to floating dynamic node in the evaluation phase. In general, except for the first stage, the evaluation network is OFF during pre-charge phase when the domino logic circuits are connected in a cascade manner.…”

Section: Introductionmentioning

confidence: 99%

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Noise measurement in high-speed domino pseudo-CMOS keeper

Poongodi

2018

Measurement and Control

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Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“…Figure 7 shows the two-input OR gate with domino logic with complement CLK keeper 15 circuit. When clk = “0,” the dynamic node is pre-charged to V DD through the MP2 transistor.…”

Section: Limitations Of Existing Keeper–based Domino Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Noise measurement in high-speed domino pseudo-CMOS keeper

Poongodi

2018

Measurement and Control

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“…In pre-charge phase, the low clock input makes the output to remain high irrespective of inputs. During evaluation phase the clock input remains high which enables pull-down network of the dynamic circuits resulting in the actual evaluation of the input logic [1], [2]. One of the major requirements for dynamicgates is monotonicity.…”

Section: Introductionmentioning

confidence: 99%

High Performance Robust Keeper Design Technique for Wide Fan-In Domino OR Logic Using CNTFET 16nm Node Technology

Ramakrishna¹,

Aswatha²

2019

IJRTE

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This paper deals with the proposed adaptable threshold keeper&dynamic buffer technique(ATKDB) for CNTFET based wide fan in domino OR logic which simultaneously reduces the average power and propagation delay of the wide fan in logic implementationcompared to various dominogatetopologies.The proposed technique provides adaptable threshold voltage for the keeper transistor by means of a designed body bias generator which drives thebulk of the keeper and there by regulates the power. The design also includes a dynamic buffer at the output node to reduce pre-charge phase power consumption. With this technique, threshold voltage for keeper device is varied dynamically to reduce the contention current and clock loading. The proposed system was tested for 16 and 32 input domino gate using 16nm CNTFET model andthesatisfactoryresults w.r.t po wer an d del ay wereobtained.

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A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates

Kumar

Nagaria

2019

Analog Integr Circ Sig Process

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A new low-power dynamic circuit for wide fan-in gates

Cited by 24 publications

References 21 publications

Noise measurement in high-speed domino pseudo-CMOS keeper

Noise measurement in high-speed domino pseudo-CMOS keeper

High Performance Robust Keeper Design Technique for Wide Fan-In Domino OR Logic Using CNTFET 16nm Node Technology

A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates

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