A New Nano Design for Implementation of a Digital Comparator Based on Quantum-Dot Cellular Automata

Optimal design for digital comparator using QCA nanotechnology with energy estimation

“…An optimized digital comparator consisting 31 QCA cells with 0.75 clock latency has been reported in Reference 29. The structure is based on inverter and majority gates.…”

Design and analysis of single layer quantum dot-cellular automata based 1- bit comparators

“…Evidently, the diversity of QCA-based logic and memory structures is introducing QCA technology as an important candidate for future computing systems. In this context, the comparator is a critical component in a plethora of digital applications including processors, microcontrollers and digital communication systems [24]- [26]. It has the function of defining three states of two n-bit numbers, which may be provided in serial or parallel manner, and then comparing and providing three possible cases: equal, larger, or smaller than each other [24]- [27].…”

“…Their implemented QCA-based comparator reduces cell count, occupied area, latency and cost with respect to earlier existing structures. More recently, Gao et al [26] have proposed a 1-bit QCA comparator utitlizing a single layer and 31 QCA cells with an occupational area of 0.04 μm 2 . Their proposed structure has required two AND gates, one OR gate and three inverters.…”

Design of Area Efficient Single Bit Comparator Circuit using Quantum dot Cellular Automata and its Digital Logic Gates Realization

“…In this paper, we have discussed another building block, i.e., comparators (1-bit). A novel design of a 1-bit comparator has been proposed and then compared against the previously available comparators [7][8][9][10][11][12][13][14][15][16][17][18].…”