A new RF architecture for cesium frequency standards

Karlquist, R.K.

doi:10.1109/freq.1992.270023

Cited by 10 publications

(4 citation statements)

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“…The frequency synthesizer is a crucial component of cesium clocks, bridging the frequency of electronic oscillator and atomic transition frequency. The stability of a clock is particularly related to the phase noise level and the settling time of the synthesized microwave signal [9][10][11][12][13]. However, we found that the vast majority of existing work in this field mainly focuses on the low phase noise of frequency synthesizers [14][15][16][17][18][19], and there are few reports on the settling time.…”

Section: Introductionmentioning

confidence: 98%

“…However, we found that the vast majority of existing work in this field mainly focuses on the low phase noise of frequency synthesizers [14][15][16][17][18][19], and there are few reports on the settling time. Therefore, in this paper, the settling time of the frequency synthesizers will be investigated in detail, which is also important for precisely identifying the central transition lines and maximizing atomic transitions [12,13].…”

Section: Introductionmentioning

confidence: 99%

“…In this design, a direct 9.192 631 770 GHz frequency signal is generated through the dielectric resonant oscillator (DRO) in the phaselocked Loop (PLL). In contrast to previous synthesizers [12][13][14][15][16][17], the dual-phase-locked loop circuits are equipped with two oven-controlled crystal oscillators (OCXOs): one serves as the 10 MHz reference source in the first PLL, and the other one operates at 200 MHz and is used in the second PLL. The 200 MHz OCXO serves the purpose of decreasing the phase noise of the intermediate frequency offset frequency band signal.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Implementation of a Frequency Synthesizer Based on Dual Phase-Locked Loops in Cesium Atomic Clock

Guo

Hou

et al. 2023

Applied Sciences

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The frequency synthesizer plays a crucial role in atomic clock technology. In this study, we demonstrate a direct microwave frequency synthesizer for a cesium atomic clock, employing frequency multiplication and a dual-phase-locked loop mode. A mathematical model of the frequency synthesis chain is established to estimate its performance. The phase-settling time and system stability are analyzed and studied in detail, and the obtained results are verified by experiments. An optimized realization of the frequency synthesizer shows that the phase-settling time can be adjusted within the range of 644.5 µs to 1.5 ms. Additionally, we measure the absolute phase noise values to be −63.7 dBc/Hz, −75.7 dBc/Hz, −107.1 dBc/Hz, and −122.5 dBc/Hz at 1 Hz, 10 Hz, 1 kHz, and 10 kHz offset frequencies, respectively.

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Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analysis and Implementation of a Frequency Synthesizer Based on Dual Phase-Locked Loops in Cesium Atomic Clock

Guo

Hou

et al. 2023

Applied Sciences

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“…5). They are then summed together to generate a stepped sine wave as in [2]. This suppresses the 3rd, and 5th harmonics, making filtering easier.…”

Section: M/n Svnthesizermentioning

confidence: 99%

A 3 to 30 MHz high-resolution synthesizer consisting of a DDS, divide-and-mix modules, and a M/N synthesizer

Karlquist

Proceedings of 1996 IEEE International Frequency Control Symposium

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A 3 to 30 MHz synthesizer is described that uses divide and mix modules to clean up the output of a DDS resulting in a building block signal source that generates an output at 10.7 MHz with a 4.2% tuning range. The divide and mix modules are based on a previously described narrowband design that has been modified for greater tuning range. Both the old and new designs exploit inexpensive ceramic filters that are normally used in the IF stages of radio receivers. The basic 10.7 MHz band is applied to an Mm synthesizer to produce an output band from 3 to 30 MHz. Various techniques for filtering harmonics from the frequency divider output are discussed, as well as circuit design details of the IO. 7 MHz mixers and filters. A PLL version of the M/N synthesizer is described that covers the band from 240 to 700 MHz, again starting from the 10.7 MHz input.

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Cs frequency synthesis: a new approach

Gupta

Popović

Walls

2000

IEEE Trans. Ultrason., Ferroelect., Freq. Contr.

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The paper describes a new approach to synthesizing the Cs hyperfine frequency of 9.192 GHz that is designed to be sufficiently rugged for use in space, specifically for the Primary Atomic Reference Clock in Space (PARCS) planned for the International Space Station, as well as ground applications. This new approach requires no narrow band filters or frequency multiplication, and the primary source of cooling is conduction. Instead of frequency multiplication, it uses a custom regenerative divider stage followed by two commercial binary dividers and several mixing stages. A fractional frequency step of 2x10(-17) is achieved by mixing the output of a 48-bit numerically controlled oscillator with the microwave signal. Preliminary tests on the new synthesizer design indicate an internal fractional frequency stability of 1x10(-15) at 10 s and 1x10 (-18) at 1 d, dominated by the daily room temperature variations. The phase and amplitude noise are similar to our previous designs that used frequency multiplication and narrow band filters. The temperature coefficient is less than 0.2 ps/K.

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A new RF architecture for cesium frequency standards

Cited by 10 publications

References 5 publications

Analysis and Implementation of a Frequency Synthesizer Based on Dual Phase-Locked Loops in Cesium Atomic Clock

Analysis and Implementation of a Frequency Synthesizer Based on Dual Phase-Locked Loops in Cesium Atomic Clock

A 3 to 30 MHz high-resolution synthesizer consisting of a DDS, divide-and-mix modules, and a M/N synthesizer

Cs frequency synthesis: a new approach

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