A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage of Faulty Nodes, Not Always Detour

Abstract

Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable Network-on-Chip (NoC) systems with high communication performance. In this chapter, we introduce a novel approach for the design of fault-tolerant routing algorithms in NoCs. The common idea of the fault-tolerant routing has been undoubtedly to detour faulty nodes, while our approach allows passing through faulty nodes with the slight modification of NoC architecture. As a design example, we present an XY-based routing algorithm with the passage function. To investigate the effect of the approach, we compare the communication performance (i.e. average latency) of the XY-based algorithm with well-known region-based algorithms under the condition of with and without virtual channels. Finally, we provide possible directions of future research on the fault-tolerant routing with the passage function.

Design of fault tolerant algorithm for network on chip router using field programmable gate array

“…Any routing method should aim to transport packets to their destinations, distribute network traffic so as to minimize packet interference, choose a short route, reduce packet delays, and ultimately improve network performance. The routing algorithms have a major significance in NoCs as it plays crucial role on the performance, complexity and implementation cost of NoC [4], [5]. There can be broadly classified depending upon the routing decisions made into deterministic routing, in which data packets take fixed pathway towards destination based on designated standards and adaptive routing, in which the pathway depends on the network conditions.…”

“…A single faulty node disrupts data packet routing which results in the failure of the entire NoC system. Therefore, the development of fault-tolerant NoC become one of the research areas in SoC-based design [5], [6]. In this work, a fault tolerant routing algorithm is developed and applied to a 4×4 mesh based NoC router architecture to validate the algorithm.…”