A Novel Architecture for Multiplier and Accumulator unit by using Parallel Prefix Adders

Abstract

MAC unit is mostly demanded in the DSP application. It performs the both addition and multiplication. Here the MAC unit is designed by using the parallel prefix adders like kogge-Stone adder, Brent-Kung adder, Han-Carlson adder and Ladner Fischer adder these adders are the high-speed adders to improve the speed of MAC unit and multiplication purpose. In this design, these four adders are implemented to the array multiplier and to design the MAC unit. The performance and analysis of MAC unit is done by the Verilog HDL and the MAC unit is simulated and synthesized in Xilinx ISE 14.7 for Spartan-6 family technology. The simulation results show that low power, high speed and low area consumption MAC unit.