A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells

First Demonstration of Reconfigurable Threshold Logic Gate using FeFET

“…To achieve various Boolean functions, we employed an algorithm from our prior research [2] to determine the FeFETs' polarization states within the LIN and RIN components of the R-TLG. Using HSPICE for verifying Boolean function truth tables, this algorithm systematically explores four distinct V TH states of FeFETs.…”

“…The circuit diagram depicted in Fig. 1 shows an R-TLG cell [2], consisting of four primary components: the left input network (LIN), the right input network (RIN), a sense amplifier (SA), and a latch (LA). LIN and RIN receive input signals as (x l1 ,....,x ln ) and (x r1 ,....,xrn) respectively, with each MOSFET in series with a FeFET.…”

“…( 1), in which the predicate is evaluated by direct comparison of electrical quantities corresponding to the two sides of the inequality. In the most recent implementations of threshold logic gates (TLG) [1], [2], the output is determined by which one of two current paths discharges two corresponding nodes first. The resulting voltage difference is sensed by a sense amplifier.…”

“…For the reconfigurability, [2] employed flash transistors, successfully implementing all 117 Boolean functions of five variables and their NPN equivalents (which number in the thousands). Here, the V TH of flash transistors acts as a stand-in for the weights.…”

“…FeFET polarization states to threshold weights mapping employed using an algorithm from our previous work[2] …”