A Novel Charge Pump with Ultra-Low Current Mismatch and Variation for PLL

Ji, Shujiang; Zhao, Yuxiao; Xu, Wilsun; Yan, Na; Min, Hao

doi:10.1109/iscas45731.2020.9180830

Cited by 10 publications

(2 citation statements)

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“…Where B i and CB are the average discharge current and parasitic capacitance at node B respectively. And the pulse width of Q can be expressed as (6).…”

Section: Clk1 Leads Clk2mentioning

confidence: 99%

“…Static phase offset will occur due to the current mismatch of charge pump [4]. So the charge pump requires additional circuitry to improve current matching, which increases design complexity [5,6]. TSPC phase detector without reset path can detect a phase difference below 10ps, and reduces the requirement for the current matching of charge pump [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

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Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

Wu,

Huang,

Sun

et al. 2023

J. Phys.: Conf. Ser.

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This work presents a phase detector (PD) having dead-zone free and static phase offset improvement performance. The proposed phase detector inherits the low power consumption advantage of the conventional phase detector using two true-single-phase clocking (TSPC) DFFs. It also effectively reduces the static phase offset, even in the presence of inevitable charge pump current mismatch. And the dead-zone problem of conventional TSPC PD is overcome by using a falling edge delay inverter. The PD is implemented using a standard 180nm CMOS technology. The dimension of the PD’s layout is 11μm×16μm. Post-layout simulation shows that the power consumption is 53.8μW at 250MHz and 160μW at 800MHz. It achieves tiny static phase offset even if the charge pump has a 3.8% current mismatch.

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“…Where B i and CB are the average discharge current and parasitic capacitance at node B respectively. And the pulse width of Q can be expressed as (6).…”

Section: Clk1 Leads Clk2mentioning

confidence: 99%