A novel design and analysis of comparator with XNOR gate for QCA

Deng, Fengbin; Xie, Guangjun; Zhang, Yongqiang; Peng, Fei; Lv, Hongjun

doi:10.1016/j.micpro.2017.10.009

Cited by 42 publications

(21 citation statements)

References 7 publications

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“…Number of XNOR gates have been proposed and compared for better performance 26 . The best performing XNOR gate has been utilized for digital comparator which consists 42 QCA cells with 0.75 clock latency.…”

Section: Previous Related Workmentioning

confidence: 99%

“…There is no reported work in the literature which has been analyzed for energy dissipation for the digital comparator using QCA Pro. One existing work reported the energy dissipation only for XNOR circuit which is further used for making the digital comparator 26 . The total energy dissipations for best reported XNOR are 56.32, 71.91 and 91.49 meV at 0.5, 1.0, 1.5 E K Kink energy levels.…”

Section: Comparison and Analysismentioning

confidence: 99%

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Optimal design for digital comparator using QCA nanotechnology with energy estimation

Sharma

2020

Int J Numerical Modelling

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Quantum‐dot cellular automata (QCA) is a transistor‐less technology to implement the nanoscale circuit designs. QCA circuits are fast, highly dense and dissipate less energy as compared to widely used complementary metal oxide semiconductor (CMOS) technology. In this paper, a novel structure for digital comparator using QCA nanotechnology is proposed. Digital comparator is a basic and important module in central processing unit which compares two binary numbers. The proposed digital comparator is optimal, single layered with 0.50 clock latency and containing only 26 QCA cells. The proposed digital comparator is compared for the different performance metrics with the existing digital comparators. The calculations for energy dissipation are provided using QCA Designer‐E and QCA Pro tools. The proposed coplanar digital comparator is designed with minimum QCA cells which reduces the total cell area, total covered area and cost. Total cell area, total covered area and cost for the proposed digital comparator are 0.008 μm2, 0.023 μm2 and 0.006 respectively. Results show that energy dissipation for the proposed design is very less therefore, proposed digital comparator is energy efficient.

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Section: Previous Related Workmentioning

confidence: 99%

Section: Comparison and Analysismentioning

confidence: 99%

Optimal design for digital comparator using QCA nanotechnology with energy estimation

Sharma

2020

Int J Numerical Modelling

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“…The cross structure can ensure the normal transmission of two routes of information. The most commonly used gates in QCA are majority gates and inverters [5][6][7]. The expression for the three-input majority gate is…”

Section: Qca Basic Componentsmentioning

confidence: 99%

“…QCA was first proposed by Lent et al in 1993 [3] and is a nanodevice based on quantum cells [4]. Due to extremely low power consumption [5] and dissipation, high device packing density, high operating speed (THz), and inherent pipeline characteristics have caused it to attract widespread attention in recent years [6][7][8][9]. The position of the quantum dot is occupied by electrons and binary information is encoded without any current flowing between the cells.…”

Section: Introductionmentioning

confidence: 99%

Implementation of the new SCV method in quantum‐dot cellular automata

Chen

Wang

Xie

2020

IET Circuits, Devices & Systems

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Quantum-dot cellular automata (QCA) is a novel nanodevice that implements logic circuits at the nanoscale. Information encryption is a key issue in nanocommunications. This article proposes a new method 'select, cross, variation' (SCV) for data encryption. This work also implements the QCA layout of this method for the first time. The QCA-based SCV circuit uses 71 cells. The circuit is composed of six majority gates and two inverters. The total area of the QCA circuit is 0.08 μm 2. The area of all the Cells' is 0.025 m 2 , accounting for 31.19% of the total area. The circuit delay is 1 clock cycle. In addition, no cross wires are used in the circuit. Comparing the theoretical values with the simulation results of QCADesigner, the design accuracy of the circuit is verified. The circuit's computational capabilities under thermal randomness is estimated, thus establishing the stability of the proposed circuit. The estimation of energy dissipation proves that the proposed circuit consumes very low energy.

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“…The concept of QCA clocking is briefly described in details in [12,18,19]. In this regard, QCA has received a numerous attention for the past few years in the logic design specially towards arithmetic logic such as adders [20,21], multiplexer [22][23][24][25], XOR [26][27][28], parity checker [29][30][31], comparators [32][33][34][35][36][37][38][39][40]. Among them, comparators have received a considerable interest as it is having an important role in the development of central processing unit (CPU) and also widely studied.…”

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confidence: 99%

Regular clocking scheme based design of cost-efficient comparator in QCA

Pal

Noorallahzadeh

Sharma

et al. 2021

IJEECS

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<span>Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.</span>

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A novel design and analysis of comparator with XNOR gate for QCA

Cited by 42 publications

References 7 publications

Optimal design for digital comparator using QCA nanotechnology with energy estimation

Optimal design for digital comparator using QCA nanotechnology with energy estimation

Implementation of the new SCV method in quantum‐dot cellular automata

Regular clocking scheme based design of cost-efficient comparator in QCA

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