A Novel Encoding Scheme for Low Power in Network on Chip Links

Abstract

Dynamic power dissipation in interconnects is a major contributor to power consumption in Network on Chips (NoCs). This is mainly due to two factors, self switching activity of the particular link and coupling switching activity among adjacent links. Two novel techniques are proposed to reduce power consumption due to switching transition and crosstalk. First technique reorders the data in such a way that switching transition is brought down. In the second technique, it is ensured that power consumption due to cross coupling activity is reduced. An end to end encoding scheme facilitating two stage coding to reduce power consumption in wormhole routed network on chip is designed using the proposed power reduction techniques. Encoder and Decoder exhibiting the proposed scheme have been described in RTL level in Verilog HDL, synthesized and mapped into UMC180 nm technology library. It has been observed that the proposed technique (TSC) offers an average reduction in dynamic power consumption of 17.34%. Proposed scheme was compared with existing techniques and observations concluded that there was not much degradation in area, speed and static power dissipation. Power reduction when subjected to different kinds of data streams was analyzed and results indicate that proposed scheme offers uniform power reduction irrespective of the nature of data stream unlike the existing techniques.