A novel fixed-outline floorplanner with zero deadspace for hierarchical design

He, Ou; Dong, Sheqin; Bian, Jinian; Goto, Satoshi; Cheng, Chung‐Kuan

doi:10.1109/iccad.2008.4681546

Cited by 4 publications

(3 citation statements)

References 17 publications

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“…The simulations are performed using the design flow given in Figure 8. The Table 3 show comparison results of Analytical floorplanning (A-FP) [33], Parquet 4.0 [34], Partitioning to optimize module arrangement (PATOMA) [35], Simulated Annealing based Fixed-outline Floorplanner with the Optimal Area (SAFFOA) [36] and SKB-tree [31] using GSRC benchmarks with average reduction in wirelength of 41.96%. The results show that SKB tree performs better compared to existing floorplanners.…”

Section: Simulation Resultsmentioning

confidence: 99%

Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

et al. 2018

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Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.

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Section: Simulation Resultsmentioning

confidence: 99%

Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

et al. 2018

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“…Based on SA algorithm, various approaches are proposed to improve the algorithm efficiency [50][51][52][53][54]. Based on SA algorithm, various approaches are proposed to improve the algorithm efficiency [50][51][52][53][54].…”

Section: Floorplanning Implementation Detailsmentioning

confidence: 99%

“…SA algorithm is the most popular method of solving floorplanning problems. Based on SA algorithm, various approaches are proposed to improve the algorithm efficiency [50][51][52][53][54]. However, the main drawback is that these techniques do not have a good scalability.…”

Section: Floorplanning Implementation Detailsmentioning

confidence: 99%

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Chu

Xia

Wang

et al. 2015

Circuit Theory & Apps

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Multi-voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire-bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi-voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time-consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency.decoupling capacitors configuration to alleviate the power delivery noise [12,13]. However, those techniques are implemented only when the floorplan or placement is ready. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. Once the voltage drops aware floorplan is obtained, the detailed P/G network design can be performed in the subsequent placement and routing stages that consider Steiner tree construction and electromigration issues [18,19].It is reported that 5% of voltage decrease may cause the circuit performance slowdown up to 15% or more [20]. Hence, designers typically limit the voltage drops within 10% of the supply voltage to guarantee faultless operation [21]. Lower supply voltage indicates that lower noise margins or smaller voltage drops are permitted on the P/G network [22]. For instance, 1.5-V supply voltages permit 150-mV voltage drop while 1.0-V supply voltages only allow 100-mV voltage drop. Compared with single-voltage SoC, the voltage drop constraints present more challenges for the P/G network design of the multi-voltage SoC. First, from a low-power perspective, a VI with a larger area and a lower supply voltage is preferred during the VI generation process. However, the permitted ultra-low voltage drops make the P/G network hard to design. Second, power pads are located at the periphery of the chip for wire-bonding package. Locations of power pads affect both the timing and voltage drops [23]. Although multiple power pads for each VI can leverage the voltage drops, it may not be practical because the power pads must compete with other signal I/Os under the limited pad resource. Thus, it is vital to consider voltage drops in P/G network design for multi-voltage SoC. Related workConsid...

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Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine

Chu

Xia

Wang

et al. 2014

Microelectronics Journal

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A novel fixed-outline floorplanner with zero deadspace for hierarchical design

Cited by 4 publications

References 17 publications

Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine

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