A novel hardware architecture of deblocking filter in H.264/AVC

Ayadi, Lella Aicha; Dammak, Taheni; Loukil, Hassen; Nouri, Mohammad

doi:10.1109/sta.2013.6783174

Cited by 1 publication

(3 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To begin, equation ( 11) is presented. The equation ( 11) result is rounded off and multiplied by the e value for both sets, as defined in (12).…”

Section: B Dual Self-guided Filter (Dsgf)mentioning

confidence: 99%

“…Finally, the Restore module concludes the filtering operation using α, β and CS global inputs and v 1 and v 2 values calculated in the previous modules to generate the four filtered CS samples according to equations (12) to (14). This module uses eight multipliers, four dividers and 16 adders to reach the desired throughput.…”

Section: B Dual Self-guided Filter Architecturementioning

confidence: 99%

“…The H.264/AVC [5] In-loop filtering at the decoder side is represented by the DBF, which is considered a complex stage since it consumes 30% of the decoder computational effort (entropy decoding with 19%, inverse quantization with 20%, predictions with 9% and others with 22%) [12]. In HEVC, only the DBF (which is not the only In-loop filter in this standard) consumes 20% of the decoder computational effort [13].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

Palau

Penny

Viana

et al. 2023

JICS

View full text Add to dashboard Cite

This paper presents a high-throughput hardware design for the Switchable Loop Restoration Filter (SLRF) of the AOM Video 1 (AV1) video format. This hardware includes the two filters defined at the AV1 SLRF: the Separable Symmetric Normalized Wiener Filter (SSNWF) and the Dual Self- Guided Filter (DSGF). The SLRF is the last step in the AV1 loop restoration filters, and it is used to attenuate blurring artifacts, improving the subjective video quality and the coding efficiency. The designed hardware targeted the AV1 decoderand is able to process up to 4K Ultra-High Definition (4K UHD) videos (with 3840x2160 pixels) at 60 frames per second (fps) in real-time. In order to cover different scenarios, two other target throughputs were also evaluated: 4K UHD at 30fps and Full HD (FHD) (with 1920x1080 pixels) at 30fps. The architectures were synthesized for standard cells using the 40 nm TSMC library. The SSNWF and DSGF architectures used 37.38 Kgates and 177.58 kgates in all evaluated scenarios. Depending on the evaluated scenario, the SSNWF power dissipation varied from 8.25mWto 26.95mWand the DSGF power varied from 57.19 mW to 115.02 mW. This is the first paper in the literature presenting a hardware design for the AV1 SLRF with its two filters.

show abstract

“…To begin, equation ( 11) is presented. The equation ( 11) result is rounded off and multiplied by the e value for both sets, as defined in (12).…”

Section: B Dual Self-guided Filter (Dsgf)mentioning

confidence: 99%

Section: B Dual Self-guided Filter Architecturementioning

confidence: 99%